| Message ID | 20250317170625.1142870-8-cleger@rivosinc.com |
|---|---|
| State | Superseded |
| Headers | show
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From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>,
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linux-kselftest@vger.kernel.org
Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>,
Samuel Holland <samuel.holland@sifive.com>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v4 07/18] riscv: misaligned: use correct CONFIG_ ifdef for
misaligned_access_speed
Date: Mon, 17 Mar 2025 18:06:13 +0100
Message-ID: <20250317170625.1142870-8-cleger@rivosinc.com>
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|
| Series |
riscv: add SBI FWFT misaligned exception delegation support
|
expand
|
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 4584f2e1d39d..8175b3449b73 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -362,7 +362,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); -#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS +#ifdef CONFIG_RISCV_SCALAR_MISALIGNED *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED; #endif