[v2,3/9] RISC-V: KVM: Add support for Raw event v2

Message ID	20250115-pmu_event_info-v2-3-84815b70383b@rivosinc.com
State	Superseded
Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: Atish Patra <atishp@rivosinc.com> Date: Wed, 15 Jan 2025 10:30:43 -0800 Subject: [PATCH v2 3/9] RISC-V: KVM: Add support for Raw event v2 MIME-Version: 1.0 Message-Id: <20250115-pmu_event_info-v2-3-84815b70383b@rivosinc.com> References: <20250115-pmu_event_info-v2-0-84815b70383b@rivosinc.com> In-Reply-To: <20250115-pmu_event_info-v2-0-84815b70383b@rivosinc.com> To: Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Mayuresh Chitale <mchitale@ventanamicro.com> Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@rivosinc.com>, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra <atishp@rivosinc.com> preview: SBI v3.0 introuced a new raw event type v2 for wider mhpmeventX programming. Add the support in kvm for that. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/kvm/vcpu_pmu.c \| 4 ++++ 1 file changed, 4 insertions(+) Content analysis details: (-1.9 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:62c listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	Add SBI v3.0 PMU enhancements \| expand [v2,0/9] Add SBI v3.0 PMU enhancements [v2,1/9] drivers/perf: riscv: Add SBI v3.0 flag [v2,2/9] drivers/perf: riscv: Add raw event v2 support [v2,3/9] RISC-V: KVM: Add support for Raw event v2 [v2,4/9] drivers/perf: riscv: Implement PMU event info function [v2,5/9] drivers/perf: riscv: Export PMU event info function [v2,6/9] KVM: Add a helper function to validate vcpu gpa range [v2,7/9] RISC-V: KVM: Use the new gpa range validate helper function [v2,8/9] RISC-V: KVM: Implement get event info function [v2,9/9] RISC-V: KVM: Upgrade the supported SBI version to 3.0

Message ID

20250115-pmu_event_info-v2-3-84815b70383b@rivosinc.com

State

Superseded

Headers

From: Atish Patra <atishp@rivosinc.com>
Date: Wed, 15 Jan 2025 10:30:43 -0800
Subject: [PATCH v2 3/9] RISC-V: KVM: Add support for Raw event v2
MIME-Version: 1.0
Message-Id: <20250115-pmu_event_info-v2-3-84815b70383b@rivosinc.com>
References: <20250115-pmu_event_info-v2-0-84815b70383b@rivosinc.com>
In-Reply-To: <20250115-pmu_event_info-v2-0-84815b70383b@rivosinc.com>
To: Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
 Mark Rutland <mark.rutland@arm.com>,
 Paul Walmsley <paul.walmsley@sifive.com>,
 Palmer Dabbelt <palmer@dabbelt.com>,
 Mayuresh Chitale <mchitale@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org,
 linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@rivosinc.com>,
 kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
 Atish Patra <atishp@rivosinc.com>
Precedence: list
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Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org>
Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org

Series

Add SBI v3.0 PMU enhancements | expand

Commit Message

Atish Patra Jan. 15, 2025, 6:30 p.m. UTC

SBI v3.0 introuced a new raw event type v2 for wider mhpmeventX
programming. Add the support in kvm for that.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kvm/vcpu_pmu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
index 2707a51b082c..efd66835c2b8 100644
--- a/arch/riscv/kvm/vcpu_pmu.c
+++ b/arch/riscv/kvm/vcpu_pmu.c
@@ -60,6 +60,7 @@  static u32 kvm_pmu_get_perf_event_type(unsigned long eidx)
 		type = PERF_TYPE_HW_CACHE;
 		break;
 	case SBI_PMU_EVENT_TYPE_RAW:
+	case SBI_PMU_EVENT_TYPE_RAW_V2:
 	case SBI_PMU_EVENT_TYPE_FW:
 		type = PERF_TYPE_RAW;
 		break;
@@ -128,6 +129,9 @@  static u64 kvm_pmu_get_perf_event_config(unsigned long eidx, uint64_t evt_data)
 	case SBI_PMU_EVENT_TYPE_RAW:
 		config = evt_data & RISCV_PMU_RAW_EVENT_MASK;
 		break;
+	case SBI_PMU_EVENT_TYPE_RAW_V2:
+		config = evt_data & RISCV_PMU_RAW_EVENT_V2_MASK;
+		break;
 	case SBI_PMU_EVENT_TYPE_FW:
 		if (ecode < SBI_PMU_FW_MAX)
 			config = (1ULL << 63) | ecode;

[v2,3/9] RISC-V: KVM: Add support for Raw event v2

Commit Message

Patch