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Fri, 21 Jun 2024 02:32:34 -0700 (PDT) Received: from J9GPGXL7NT.bytedance.net ([61.213.176.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7065124dd26sm968415b3a.127.2024.06.21.02.32.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 21 Jun 2024 02:32:33 -0700 (PDT) From: Xu Lu To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor.dooley@microchip.com, anup@brainfault.org, atishp@atishpatra.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, christoph.muellner@vrull.eu, heiko@sntech.de, charlie@rivosinc.com, David.Laight@aculab.com, parri.andrea@gmail.com, Xu Lu Subject: [RFC v2 0/2] riscv: Idle thread using Zawrs extension Date: Fri, 21 Jun 2024 17:32:21 +0800 Message-Id: <20240621093223.37893-1-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240621_023239_907469_C3FD44F7 X-CRM114-Status: UNSURE ( 8.57 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This is the second version of idle thread based on Zawrs extension. We rebased our code on Andrew's patch series[1] which provides basic support for Zawrs as well as optimization for spinlock. This patch series introduces a new implementation of idle thread using Zawrs extension. Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:22c listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This is the second version of idle thread based on Zawrs extension. We rebased our code on Andrew's patch series[1] which provides basic support for Zawrs as well as optimization for spinlock. This patch series introduces a new implementation of idle thread using Zawrs extension. The Zawrs[0] extension introduces two new instructions named WRS.STO and WRS.NTO in RISC-V. When software registers a reservation set using LR instruction, a subsequent WRS.STO or WRS.NTO instruction will cause the hart to stall in a low-power state until a store happens to the reservation set or an interrupt becomes pending. The difference between these two instructions is that WRS.STO will terminate stall after an implementation-defined timeout while WRS.NTO won't. This patch series implements idle thread using WRS.NTO instruction. Besides, we found there is no need to send a real IPI to wake up an idle CPU. Instead, we write IPI information to the reservation set of an idle CPU to wake it up and let it handle IPI quickly, without going through tranditional interrupt handling routine. [0] https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc [1] https://github.com/jones-drew/linux/commits/riscv/zawrs-v3 Xu Lu (2): riscv: process: Introduce idle thread using Zawrs extension riscv: Use Zawrs to accelerate IPI to idle cpu arch/riscv/Kconfig | 10 +++ arch/riscv/include/asm/cpuidle.h | 11 +--- arch/riscv/include/asm/processor.h | 32 +++++++++ arch/riscv/include/asm/smp.h | 14 ++++ arch/riscv/kernel/cpu.c | 5 ++ arch/riscv/kernel/process.c | 102 ++++++++++++++++++++++++++++- arch/riscv/kernel/smp.c | 39 +++++++---- 7 files changed, 190 insertions(+), 23 deletions(-)