| Message ID | 20241115141736.627079-1-tore@amundsen.org |
|---|---|
| State | Accepted |
| Delegated to: | Anthony Nguyen |
| Headers | show |
| Series | [v3,1/1] ixgbe: Correct BASE-BX10 compliance code | expand |
> -----Original Message----- > From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Tore Amundsen > Sent: 15 November 2024 19:48 > To: netdev@vger.kernel.org > Cc: pmenzel@molgen.mpg.de; andrew+netdev@lunn.ch; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; davem@davemloft.net; edumazet@google.com; ernesto@castellotti.net; intel-wired-lan@lists.osuosl.org; kuba@kernel.org; linux-kernel@vger.kernel.org; pabeni@redhat.com; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; tore@amundsen.org > Subject: [Intel-wired-lan] [PATCH v3 1/1] ixgbe: Correct BASE-BX10 compliance code > > SFF-8472 (section 5.4 Transceiver Compliance Codes) defines bit 6 as BASE-BX10. Bit 6 means a value of 0x40 (decimal 64). > > The current value in the source code is 0x64, which appears to be a mix-up of hex and decimal values. A value of 0x64 (binary 01100100) incorrectly sets bit 2 (1000BASE-CX) and bit 5 (100BASE-FX) as well. > > Fixes: 1b43e0d20f2d ("ixgbe: Add 1000BASE-BX support") > Signed-off-by: Tore Amundsen <tore@amundsen.org> > Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> > Acked-by: Ernesto Castellotti <ernesto@castellotti.net> > --- > v2: Added Fixes tag as requested by Paul Menzel. > v3: Correct Fixes tag format and add Acked-By. > > drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h index 14aa2ca51f70..81179c60af4e 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h @@ -40,7 +40,7 @@ #define IXGBE_SFF_1GBASESX_CAPABLE 0x1 #define IXGBE_SFF_1GBASELX_CAPABLE 0x2 #define IXGBE_SFF_1GBASET_CAPABLE 0x8 -#define IXGBE_SFF_BASEBX10_CAPABLE 0x64 +#define IXGBE_SFF_BASEBX10_CAPABLE 0x40 #define IXGBE_SFF_10GBASESR_CAPABLE 0x10 #define IXGBE_SFF_10GBASELR_CAPABLE 0x20 #define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8
SFF-8472 (section 5.4 Transceiver Compliance Codes) defines bit 6 as BASE-BX10. Bit 6 means a value of 0x40 (decimal 64). The current value in the source code is 0x64, which appears to be a mix-up of hex and decimal values. A value of 0x64 (binary 01100100) incorrectly sets bit 2 (1000BASE-CX) and bit 5 (100BASE-FX) as well. Fixes: 1b43e0d20f2d ("ixgbe: Add 1000BASE-BX support") Signed-off-by: Tore Amundsen <tore@amundsen.org> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Acked-by: Ernesto Castellotti <ernesto@castellotti.net> --- v2: Added Fixes tag as requested by Paul Menzel. v3: Correct Fixes tag format and add Acked-By. drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)