| Message ID | 20241108134143.327-1-julian.oerv@isrc.iscas.ac.cn |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] RISC-V: Use builtin for ffs and ffsll while supported extension available | expand |
Ping. Thanks. 在 2024/11/8 21:41, Julian Zhu 写道: > Hardware ctz instructions are available in the RISC-V Zbb and XTheadBb extension. With special `-march` flags defined, we can generate more simplified code compared to the generic implementation of `ffs`/`ffsll`. > > Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn> > --- > sysdeps/riscv/math-use-builtins-ffs.h | 10 ++++++++++ > 1 file changed, 10 insertions(+)
diff --git a/sysdeps/riscv/math-use-builtins-ffs.h b/sysdeps/riscv/math-use-builtins-ffs.h new file mode 100644 index 0000000000..97d13e9496 --- /dev/null +++ b/sysdeps/riscv/math-use-builtins-ffs.h @@ -0,0 +1,10 @@ +#if __GNUC_PREREQ (12, 0) && defined __riscv_zbb +# define USE_FFS_BUILTIN 1 +# define USE_FFSLL_BUILTIN 1 +#elif __GNUC_PREREQ (13, 0) && defined __riscv_xtheadbb +# define USE_FFS_BUILTIN 0 +# define USE_FFSLL_BUILTIN 1 +#else +# define USE_FFS_BUILTIN 0 +# define USE_FFSLL_BUILTIN 0 +#endif
Hardware ctz instructions are available in the RISC-V Zbb and XTheadBb extension. With special `-march` flags defined, we can generate more simplified code compared to the generic implementation of `ffs`/`ffsll`. Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn> --- sysdeps/riscv/math-use-builtins-ffs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 sysdeps/riscv/math-use-builtins-ffs.h