From patchwork Fri Oct 4 10:50:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1992701 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XKlhd5vBqz1xsn for ; Fri, 4 Oct 2024 20:51:13 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A6D6F386D606 for ; Fri, 4 Oct 2024 10:51:11 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 78124386D611 for ; Fri, 4 Oct 2024 10:50:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 78124386D611 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 78124386D611 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1728039030; cv=none; b=Hn7GuzjciGVkG2SoYwmeSKejXw5M9i2UDYC541PqN0OggeCFO/Ibm0Q0F9ZWvwk+W3hCX48Xt7paJAvdZOXN2J+udgynG13s+a+tUNb/7TlMmNq+ImNIEg6Gq44hV3LZhdGOz/S1H2IW6DYRoJ+ktD1jCVCVciTr3Svdi9PV0xI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1728039030; c=relaxed/simple; bh=eDToctk+2V4sPuOSwLcACP6G8eR/DTtN3QfxzwC1yXw=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=fu/3FQziL3YQWs8KsNZ08ItnRruEQS6JJJ7+piThkviw7WxaQD/PNjxUR0k5fbaWO872Nr3EC2XZV5k1C7O/9kBP9hUp6wbTOm+4eZu6lQkMxjKKr2NSvDKlHFGWWElM/Dx+Q3HD6Wrsn7MiQNof838jPAWkErQzsbmeow9pAWA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B86A1339; Fri, 4 Oct 2024 03:50:56 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6BDFD3F640; Fri, 4 Oct 2024 03:50:26 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org,ktkachov@nvidia.com, richard.earnshaw@arm.com, tamar.christina@arm.com, richard.sandiford@arm.com Cc: ktkachov@nvidia.com, richard.earnshaw@arm.com, tamar.christina@arm.com Subject: [PATCH] aarch64: Fix general permutes of svbfloat16_ts Date: Fri, 04 Oct 2024 11:50:25 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) MIME-Version: 1.0 X-Spam-Status: No, score=-18.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Testing gcc.target/aarch64/sve/permute_2.c without the associated GCC patch triggered an unrecognisable insn ICE for the svbfloat16_t tests. This was because the implementation of general two-vector permutes requires two TBLs and an ORR, with the ORR being represented as an unspec for floating-point modes. The associated pattern did not cover VNx8BF. Tested on aarch64-linux-gnu (with and without SVE enabled by default). I'll push on Monday if there are no comments before then. Thanks, Richard gcc/ * iterators.md (SVE_I): Move further up file. (SVE_F): New mode iterator. (SVE_ALL): Redefine in terms of SVE_I and SVE_F. * config/aarch64/aarch64-sve.md (*3): Extend to all SVE_F. gcc/testsuite/ * gcc.target/aarch64/sve/permute_5.c: New test. --- gcc/config/aarch64/aarch64-sve.md | 8 +++--- gcc/config/aarch64/iterators.md | 27 +++++++++---------- .../gcc.target/aarch64/sve/permute_5.c | 10 +++++++ 3 files changed, 27 insertions(+), 18 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/permute_5.c diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index ec1d059a2b1..90db51e51b9 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -6455,10 +6455,10 @@ (define_expand "@aarch64_frecps" ;; by providing this, but we need to use UNSPECs since rtx logical ops ;; aren't defined for floating-point modes. (define_insn "*3" - [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w") - (unspec:SVE_FULL_F - [(match_operand:SVE_FULL_F 1 "register_operand" "w") - (match_operand:SVE_FULL_F 2 "register_operand" "w")] + [(set (match_operand:SVE_F 0 "register_operand" "=w") + (unspec:SVE_F + [(match_operand:SVE_F 1 "register_operand" "w") + (match_operand:SVE_F 2 "register_operand" "w")] LOGICALF))] "TARGET_SVE" "\t%0.d, %1.d, %2.d" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 0836dee61c9..0f19cae73c9 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -519,15 +519,20 @@ (define_mode_iterator SVE_PARTIAL_I [VNx8QI VNx4QI VNx2QI VNx4HI VNx2HI VNx2SI]) +;; All SVE integer vector modes. +(define_mode_iterator SVE_I [VNx16QI VNx8QI VNx4QI VNx2QI + VNx8HI VNx4HI VNx2HI + VNx4SI VNx2SI + VNx2DI]) + +;; All SVE floating-point vector modes. +(define_mode_iterator SVE_F [VNx8HF VNx4HF VNx2HF + VNx8BF VNx4BF VNx2BF + VNx4SF VNx2SF + VNx2DF]) + ;; All SVE vector modes. -(define_mode_iterator SVE_ALL [VNx16QI VNx8QI VNx4QI VNx2QI - VNx8HI VNx4HI VNx2HI - VNx8HF VNx4HF VNx2HF - VNx8BF VNx4BF VNx2BF - VNx4SI VNx2SI - VNx4SF VNx2SF - VNx2DI - VNx2DF]) +(define_mode_iterator SVE_ALL [SVE_I SVE_F]) ;; All SVE 2-vector modes. (define_mode_iterator SVE_FULLx2 [VNx32QI VNx16HI VNx8SI VNx4DI @@ -549,12 +554,6 @@ (define_mode_iterator SVE_STRUCT [SVE_FULLx2 SVE_FULLx3 SVE_FULLx4]) ;; All SVE vector and structure modes. (define_mode_iterator SVE_ALL_STRUCT [SVE_ALL SVE_STRUCT]) -;; All SVE integer vector modes. -(define_mode_iterator SVE_I [VNx16QI VNx8QI VNx4QI VNx2QI - VNx8HI VNx4HI VNx2HI - VNx4SI VNx2SI - VNx2DI]) - ;; All SVE integer vector modes and Advanced SIMD 64-bit vector ;; element modes (define_mode_iterator SVE_I_SIMD_DI [SVE_I V2DI]) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/permute_5.c b/gcc/testsuite/gcc.target/aarch64/sve/permute_5.c new file mode 100644 index 00000000000..786b05ee3e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/permute_5.c @@ -0,0 +1,10 @@ +/* { dg-options "-O -msve-vector-bits=256" } */ + +typedef __SVBfloat16_t vbfloat16 __attribute__((arm_sve_vector_bits(256))); + +vbfloat16 +foo (vbfloat16 x, vbfloat16 y) +{ + return __builtin_shufflevector (x, y, 0, 2, 1, 3, 16, 19, 17, 18, + 8, 9, 10, 11, 23, 22, 21, 20); +}