From patchwork Mon Nov 18 06:51:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 2012621 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=jaddCFcs; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XsJGH2RJJz1xyx for ; Mon, 18 Nov 2024 17:52:20 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E52F2385841C for ; Mon, 18 Nov 2024 06:52:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E52F2385841C Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=jaddCFcs X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 28F3A3858D29 for ; Mon, 18 Nov 2024 06:51:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 28F3A3858D29 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 28F3A3858D29 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=148.163.158.5 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1731912703; cv=none; b=Auv9d1m62xZJvEWvxvrHjBsmxJYQP/QG0vmtRjjMZ+HPxMy35FDpybJkiYiMpN/kNPzy5/sn2tDCYEDKDlBuCRowQb9xXvszKja4AdminSBuoJnMWzLPhWzECgyABuyGtP3xoB/b19gmQRB3SSdSjll3j93D9jVOPafq9BQmWS0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1731912703; c=relaxed/simple; bh=nURW3wMjh5O0s6Cila5J6xN6BwimI8ttWAmfbxP1TtQ=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=Yho27idYs7iQsBA79+Xc3qtECyWhAc+aUIr9yL22YnbjS0MegxuqYYDCX0TPocWNNH3q/Ss+QIhe6iAQChiLcRcx1B3q+ex3c2+XL9FQJi96uzAVFZQs3ofE+J2Il+FIXyIkA+h60OO+wdCV9xtWTyS9kSgs7RcoQR6Pe8ZlJ5w= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 28F3A3858D29 Received: from pps.filterd (m0356516.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AHJr9QP007801; Mon, 18 Nov 2024 06:51:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h= content-type:date:from:message-id:mime-version:subject:to; s= pp1; bh=7ksDJZjGQhIa4eQqp986LpChXt5NWx34uH9/XfNSQ5I=; b=jaddCFcs TOMy0PBVGNuHGkm3IifSc6GRsXPpWpyQ1ck6LMeJrLOxATbFWPFy5J5g3NjQoRvP 049T+4YxOO6zTOpcM40sdJWpLkKVVjNwal24oSY8JuTHjsb2EDEQeVDzAYM9FrX3 8rXEjqJ0o1v3wLmZr1L+5erATcYfK+vKXvsR8kdEgLcld2LGyveDAQdlDUHR41sJ OJFuUp9bD4oO4E1wukNPKLLXy/cV96Hj2imfQLJ5hVJcUdQxpyAXGVdH4DqnE9nP m8unwGv6P2SFRe1SoKu51PxcTiIfb60HVPqEYJgEB5AgPNI9ASmHEMEwZGTj29hs KoBKHHUlSlFc2g== Received: from ppma22.wdc07v.mail.ibm.com (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 42xgtt01k7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Nov 2024 06:51:42 +0000 (GMT) Received: from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1]) by ppma22.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 4AI52W9X030931; Mon, 18 Nov 2024 06:51:41 GMT Received: from smtprelay07.wdc07v.mail.ibm.com ([172.16.1.74]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 42y63y1fee-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Nov 2024 06:51:41 +0000 Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay07.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 4AI6peuH25952772 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 18 Nov 2024 06:51:40 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5537D584DA; Mon, 18 Nov 2024 06:51:40 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 04DEC584D9; Mon, 18 Nov 2024 06:51:40 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.98.188]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTPS; Mon, 18 Nov 2024 06:51:39 +0000 (GMT) Date: Mon, 18 Nov 2024 01:51:31 -0500 From: Michael Meissner To: gcc-patches@gcc.gnu.org, Michael Meissner , Segher Boessenkool , Peter Bergner Subject: [PATCH] PR target/108958: Use mtvsrdd to zero extend GPR DImode to VSX TImode Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner MIME-Version: 1.0 Content-Disposition: inline X-TM-AS-GCONF: 00 X-Proofpoint-GUID: mZ44xwfGLwpe7Hck12gd7paYTQYlb1_V X-Proofpoint-ORIG-GUID: mZ44xwfGLwpe7Hck12gd7paYTQYlb1_V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 mlxscore=0 malwarescore=0 mlxlogscore=900 adultscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411180053 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Previously GCC would zero externd a DImode GPR value to TImode by first zero extending the DImode value into a GPR TImode value, and then do a MTVSRDD to move this value to a VSX register. This patch does the move directly, since if the middle argument to MTVSRDD is 0, it does the zero extend. If the DImode value is already in a vector register, it does a XXSPLTIB and XXPERMDI to get the value into the bottom 64-bits of the register. I have built GCC with the patches in this patch set applied on both little and big endian PowerPC systems and there were no regressions. Can I apply this patch to GCC 15? 2024-11-17 Michael Meissner gcc/ PR target/108598 * gcc/config/rs6000/rs6000.md (zero_extendditi2): New insn. gcc/testsuite/ PR target/108598 * gcc.target/powerpc/pr108958.c: New test. --- gcc/config/rs6000/rs6000.md | 46 +++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr108958.c | 27 ++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108958.c diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d266f93ff2e..bfb02b07ef4 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1026,6 +1026,52 @@ (define_insn_and_split "*zero_extendsi2_dot2" (set_attr "dot" "yes") (set_attr "length" "4,8")]) +(define_insn_and_split "zero_extendditi2" + [(set (match_operand:TI 0 "gpc_reg_operand" "=r,wa,&wa") + (zero_extend:TI + (match_operand:DI 1 "gpc_reg_operand" "rwa,r,wa")))] + "TARGET_P9_VECTOR && TARGET_POWERPC64" + "@ + # + mtvsrdd %x0,0,%1 + #" + "&& reload_completed + && (int_reg_operand (operands[0], TImode) + || vsx_register_operand (operands[1], DImode))" + [(set (match_dup 2) + (match_dup 3)) + (set (match_dup 4) + (match_dup 5))] +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + int r = reg_or_subregno (op0); + + if (int_reg_operand (op0, TImode)) + { + int lo = BYTES_BIG_ENDIAN ? 1 : 0; + int hi = 1 - lo; + + operands[2] = gen_rtx_REG (DImode, r + lo); + operands[3] = op1; + operands[4] = gen_rtx_REG (DImode, r + hi); + operands[5] = const0_rtx; + } + else + { + rtx op0_di = gen_rtx_REG (DImode, r); + rtx op0_v2di = gen_rtx_REG (V2DImode, r); + rtx lo = WORDS_BIG_ENDIAN ? op1 : op0_di; + rtx hi = WORDS_BIG_ENDIAN ? op0_di : op1; + + operands[2] = op0_v2di; + operands[3] = CONST0_RTX (V2DImode); + operands[4] = op0_v2di; + operands[5] = gen_rtx_VEC_CONCAT (V2DImode, hi, lo); + } +} + [(set_attr "type" "*,mtvsr,vecperm") + (set_attr "length" "8,*,8")]) (define_insn "extendqi2" [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*v") diff --git a/gcc/testsuite/gcc.target/powerpc/pr108958.c b/gcc/testsuite/gcc.target/powerpc/pr108958.c new file mode 100644 index 00000000000..03eb58d069e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr108958.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target int128 } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ + +/* PR target/108958, use mtvsrdd to zero extend gpr to vsx register. */ + +void +gpr_to_vsx (unsigned long long x, __uint128_t *p) +{ + /* mtvsrdd vsx,0,gpr. */ + __uint128_t y = x; + __asm__ (" # %x0" : "+wa" (y)); + *p = y; +} + +void +gpr_to_gpr (unsigned long long x, __uint128_t *p) +{ + /* mr and li. */ + __uint128_t y = x; + __asm__ (" # %0" : "+r" (y)); + *p = y; +} + +/* { dg-final { scan-assembler-times {\mli\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mmtvsrdd .*,0,.*\M} 1 } } */