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Sat, 16 Nov 2024 17:56:35 +0000 Received: from smtpav01.dal12v.mail.ibm.com (smtpav01.dal12v.mail.ibm.com [10.241.53.100]) by smtprelay06.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 4AGHuZd458786070 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 16 Nov 2024 17:56:35 GMT Received: from smtpav01.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1C7AD58064; Sat, 16 Nov 2024 17:56:35 +0000 (GMT) Received: from smtpav01.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AC76F5805D; Sat, 16 Nov 2024 17:56:34 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.98.188]) by smtpav01.dal12v.mail.ibm.com (Postfix) with ESMTPS; Sat, 16 Nov 2024 17:56:34 +0000 (GMT) Date: Sat, 16 Nov 2024 12:56:33 -0500 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner Subject: [PATCH V4 2/2] Use architecture flags for defining _ARCH_PWR macros. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Z7I8WSlWc0cj4lMr6My2wa3TE_CgP8_t X-Proofpoint-GUID: Z7I8WSlWc0cj4lMr6My2wa3TE_CgP8_t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160151 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org For the newer architectures, this patch changes GCC to define the _ARCH_PWR macros using the new architecture flags instead of relying on isa options like -mpower10. The -mpower8-internal, -mpower10, -mpower11, and -mfuture options were removed. The -mpower11 and -mfuture options were removed completely, since they were just added in GCC 15. The other two options were marked as WarnRemoved, and the various ISA bits were removed. TARGET_POWER8, TARGET_POWER10, TARGET_POWER11, and TARGET_FUTURE were re-defined to use the architeture bits instead of the ISA bits. There are other internal isa bits that aren't removed with this patch because the built-in function support uses those bits. I have built both big endian and little endian bootstrap compilers and there were no regressions. Can I install this patch on the GCC 15 trunk? 2024-11-16 Michael Meissner gcc/ * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros) Add support to use architecture flags instead of ISA flags for setting most of the _ARCH_PWR* macros. (rs6000_cpu_cpp_builtins): Update rs6000_target_modify_macros call. * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove OPTION_MASK_POWER8. (ISA_3_1_MASKS_SERVER): Remove OPTION_MASK_POWER10. (POWER11_MASKS_SERVER): Remove OPTION_MASK_POWER11. (FUTURE_MASKS_SERVER): Remove OPTION_MASK_FUTURE. (POWERPC_MASKS): Remove OPTION_MASK_POWER8, OPTION_MASK_POWER10, OPTION_MASK_POWER11, and OPTION_MASK_FUTURE. * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Update declaration. (rs6000_target_modify_macros_ptr): Likewise. * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise. (rs6000_option_override_internal): Use architecture flags instead of ISA flags. (rs6000_opt_masks): Remove -mpower10, -mpower11, and -mfuture which are no longer in the ISA flags. (rs6000_pragma_target_parse): Use architecture flags as well as ISA flags. * config/rs6000/rs6000.h (TARGET_POWER5): Redefine to use architecture flags. (TARGET_POWER5X): Likewise. (TARGET_POWER6): Likewise. (TARGET_POWER7): Likewise. (TARGET_POWER8): Likewise. (TARGET_POWER9): Likewise. (TARGET_POWER10): New macro. (TARGET_POWER11): Likewise. (TARGET_FUTURE): Likewise. * config/rs6000/rs6000.opt (-mpower8-internal): Remove ISA flag bits. (-mpower10): Likewise. (-mpower11): Likewise. (-mfuture): Likewise. --- gcc/config/rs6000/rs6000-c.cc | 29 ++++++++++++++++------------- gcc/config/rs6000/rs6000-cpus.def | 10 +--------- gcc/config/rs6000/rs6000-protos.h | 5 +++-- gcc/config/rs6000/rs6000.cc | 20 +++++++++++--------- gcc/config/rs6000/rs6000.h | 19 +++++++++++++------ gcc/config/rs6000/rs6000.opt | 17 ++--------------- 6 files changed, 46 insertions(+), 54 deletions(-) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index b0b5701c7fa..30ea1d64326 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -339,7 +339,8 @@ rs6000_define_or_undefine_macro (bool define_p, const char *name) #pragma GCC target, we need to adjust the macros dynamically. */ void -rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) +rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, + HOST_WIDE_INT arch_flags) { if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) fprintf (stderr, @@ -412,7 +413,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) summary of the flags associated with particular cpu definitions. */ - /* rs6000_isa_flags based options. */ + /* rs6000_isa_flags and rs6000_arch_flags based options. */ rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); if ((flags & OPTION_MASK_PPC_GPOPT) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); @@ -420,25 +421,27 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); if ((flags & OPTION_MASK_POWERPC64) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); - if ((flags & OPTION_MASK_MFCRF) != 0) + if ((flags & OPTION_MASK_POWERPC64) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); + if ((arch_flags & ARCH_MASK_POWER4) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); - if ((flags & OPTION_MASK_POPCNTB) != 0) + if ((arch_flags & ARCH_MASK_POWER5) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); - if ((flags & OPTION_MASK_FPRND) != 0) + if ((arch_flags & ARCH_MASK_POWER5X) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); - if ((flags & OPTION_MASK_CMPB) != 0) + if ((arch_flags & ARCH_MASK_POWER6) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); - if ((flags & OPTION_MASK_POPCNTD) != 0) + if ((arch_flags & ARCH_MASK_POWER7) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); - if ((flags & OPTION_MASK_POWER8) != 0) + if ((arch_flags & ARCH_MASK_POWER8) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8"); - if ((flags & OPTION_MASK_MODULO) != 0) + if ((arch_flags & ARCH_MASK_POWER9) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); - if ((flags & OPTION_MASK_POWER10) != 0) + if ((arch_flags & ARCH_MASK_POWER10) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); - if ((flags & OPTION_MASK_POWER11) != 0) + if ((arch_flags & ARCH_MASK_POWER11) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11"); - if ((flags & OPTION_MASK_FUTURE) != 0) + if ((arch_flags & ARCH_MASK_FUTURE) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_FUTURE"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); @@ -608,7 +611,7 @@ void rs6000_cpu_cpp_builtins (cpp_reader *pfile) { /* Define all of the common macros. */ - rs6000_target_modify_macros (true, rs6000_isa_flags); + rs6000_target_modify_macros (true, rs6000_isa_flags, rs6000_arch_flags); if (TARGET_FRE) builtin_define ("__RECIP__"); diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 62e6c9d3b58..74151be4048 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -47,7 +47,6 @@ fusion here, instead set it in rs6000.cc if we are tuning for a power8 system. */ #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ - | OPTION_MASK_POWER8 \ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ @@ -83,14 +82,11 @@ | OPTION_MASK_PREFIXED) #define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ - | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS) -#define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \ - | OPTION_MASK_POWER11) +#define POWER11_MASKS_SERVER ISA_3_1_MASKS_SERVER #define FUTURE_MASKS_SERVER (POWER11_MASKS_SERVER \ - | OPTION_MASK_FUTURE \ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR) /* Flags that need to be turned off if -mno-vsx. */ @@ -130,9 +126,6 @@ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_FLOAT128_KEYWORD \ | OPTION_MASK_FPRND \ - | OPTION_MASK_FUTURE \ - | OPTION_MASK_POWER10 \ - | OPTION_MASK_POWER11 \ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ @@ -141,7 +134,6 @@ | OPTION_MASK_MODULO \ | OPTION_MASK_MULHW \ | OPTION_MASK_NO_UPDATE \ - | OPTION_MASK_POWER8 \ | OPTION_MASK_P8_FUSION \ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_P9_MINMAX \ diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index b40557a8557..da658cd5ab2 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -323,8 +323,9 @@ extern void rs6000_cpu_cpp_builtins (struct cpp_reader *); extern bool rs6000_pragma_target_parse (tree, tree); #endif extern void rs6000_activate_target_options (tree new_tree); -extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT); -extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT); +extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT, HOST_WIDE_INT); +extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, + HOST_WIDE_INT); #ifdef NO_DOLLAR_IN_LABEL const char * rs6000_xcoff_strip_dollar (const char *); diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 603c72472b0..dc5b7eb74d4 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -278,7 +278,7 @@ bool cpu_builtin_p = false; /* Pointer to function (in rs6000-c.cc) that can define or undefine target macros that have changed. Languages that don't support the preprocessor don't link in rs6000-c.cc, so we can't call it directly. */ -void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT); +void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT); /* Simplfy register classes into simpler classifications. We assume GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range @@ -3909,8 +3909,7 @@ rs6000_option_override_internal (bool global_init_p) /* If little-endian, default to -mstrict-align on older processors. */ if (!BYTES_BIG_ENDIAN - && !(processor_target_table[tune_index].target_enable - & OPTION_MASK_POWER8)) + && (get_arch_flags (tune_index) & ARCH_MASK_POWER8) == 0) rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; /* Add some warnings for VSX. */ @@ -24605,9 +24604,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true }, { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, - { "future", OPTION_MASK_FUTURE, false, false }, - { "power10", OPTION_MASK_POWER10, false, true }, - { "power11", OPTION_MASK_POWER11, false, false }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, @@ -25039,6 +25035,7 @@ rs6000_pragma_target_parse (tree args, tree pop_target) tree cur_tree; struct cl_target_option *prev_opt, *cur_opt; HOST_WIDE_INT prev_flags, cur_flags, diff_flags; + HOST_WIDE_INT prev_arch, cur_arch, diff_arch; if (TARGET_DEBUG_TARGET) { @@ -25091,21 +25088,26 @@ rs6000_pragma_target_parse (tree args, tree pop_target) { prev_opt = TREE_TARGET_OPTION (prev_tree); prev_flags = prev_opt->x_rs6000_isa_flags; + prev_arch = prev_opt->x_rs6000_arch_flags; cur_opt = TREE_TARGET_OPTION (cur_tree); cur_flags = cur_opt->x_rs6000_isa_flags; + cur_arch = cur_opt->x_rs6000_arch_flags; diff_flags = (prev_flags ^ cur_flags); + diff_arch = (prev_arch ^ cur_arch); - if (diff_flags != 0) + if (diff_flags != 0 || diff_arch != 0) { /* Delete old macros. */ rs6000_target_modify_macros_ptr (false, - prev_flags & diff_flags); + prev_flags & diff_flags, + prev_arch & diff_arch); /* Define new macros. */ rs6000_target_modify_macros_ptr (true, - cur_flags & diff_flags); + cur_flags & diff_flags, + cur_arch & diff_arch); } } diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 382d7824064..f95318dd553 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -502,12 +502,19 @@ extern int rs6000_vector_align[]; #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && (TARGET_P9_MINMAX || !flag_trapping_math)) -/* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */ -#define TARGET_POWER5 TARGET_POPCNTB -#define TARGET_POWER5X TARGET_FPRND -#define TARGET_POWER6 TARGET_CMPB -#define TARGET_POWER7 TARGET_POPCNTD -#define TARGET_POWER9 TARGET_MODULO +/* In the past we represented the various power cpus (power4, power5, power6, + etc.) via ISA bits that highlighted a new instruction or we used an extra + option to represent the hardware (i.e. -mpower8-internal or -mpower10). Now + we use architecture flags for this. */ +#define TARGET_POWER5 ((rs6000_arch_flags & ARCH_MASK_POWER5) != 0) +#define TARGET_POWER5X ((rs6000_arch_flags & ARCH_MASK_POWER5X) != 0) +#define TARGET_POWER6 ((rs6000_arch_flags & ARCH_MASK_POWER6) != 0) +#define TARGET_POWER7 ((rs6000_arch_flags & ARCH_MASK_POWER7) != 0) +#define TARGET_POWER8 ((rs6000_arch_flags & ARCH_MASK_POWER8) != 0) +#define TARGET_POWER9 ((rs6000_arch_flags & ARCH_MASK_POWER9) != 0) +#define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0) +#define TARGET_POWER11 ((rs6000_arch_flags & ARCH_MASK_POWER11) != 0) +#define TARGET_FUTURE ((rs6000_arch_flags & ARCH_MASK_FUTURE) != 0) /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 66c432f1384..0d71dbaf2fc 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -478,9 +478,8 @@ Save the TOC in the prologue for indirect calls rather than inline. mvsx-timode Target RejectNegative Undocumented Ignore -;; This option exists only to create its MASK. It is not intended for users. mpower8-internal -Target Undocumented Mask(POWER8) Var(rs6000_isa_flags) Warn(Do not use %<-mpower8-internal%>; use %<-mcpu=power8%> instead) +Target Undocumented WarnRemoved mpower8-fusion Target Mask(P8_FUSION) Var(rs6000_isa_flags) @@ -591,13 +590,7 @@ mspeculate-indirect-jumps Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save mpower10 -Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved - -;; Users should not use -mpower11, but we need to use a bit to identify when -;; the user changes the default cpu via #pragma GCC target("cpu=power11") -;; and then resets it later. -mpower11 -Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) WarnRemoved +Target Undocumented WarnRemoved mprefixed Target Mask(PREFIXED) Var(rs6000_isa_flags) @@ -638,12 +631,6 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. -;; Users should not use -mfuture, but we need to use a bit to identify when -;; the user changes the default cpu via #pragma GCC target("cpu=future") -;; and then resets it later. -mfuture -Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) WarnRemoved - ; Documented parameters -param=rs6000-vect-unroll-limit=