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Sat, 16 Nov 2024 17:29:17 +0000 Received: from smtpav04.wdc07v.mail.ibm.com (smtpav04.wdc07v.mail.ibm.com [10.39.53.231]) by smtprelay06.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 4AGHTGxi47514090 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 16 Nov 2024 17:29:16 GMT Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5293E58050; Sat, 16 Nov 2024 17:29:16 +0000 (GMT) Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 827BD58045; Sat, 16 Nov 2024 17:29:15 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.98.188]) by smtpav04.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Sat, 16 Nov 2024 17:29:15 +0000 (GMT) Date: Sat, 16 Nov 2024 12:29:13 -0500 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner Subject: [PATCH V4 1/4] Add support for -mcpu=future in the PowerPC Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: MacTSSMb-AIjHWNLUBkT5PD3p8Modhdz X-Proofpoint-ORIG-GUID: MacTSSMb-AIjHWNLUBkT5PD3p8Modhdz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 adultscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160151 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch adds the support that can be used in developing GCC support for future PowerPC processors. I have built GCC with the patches in this patch set applied on both little and big endian PowerPC systems and there were no regressions. Can I apply this patch to GCC 15? 2024-11-15 Michael Meissner * config.gcc (powerpc*-*-*): Add support for --with-cpu=future. * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=future. * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. * config/rs6000/driver-rs6000.cc (asm_names): Likewise. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): If -mcpu=future, define _ARCH_FUTURE. * config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro. (POWERPC_MASKS): Add OPTION_MASK_FUTURE. (future cpu): Define. * config/rs6000/rs6000-opts.h (enum processor_type): Add PROCESSOR_FUTURE. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (power10_cost): Update comment. (get_arch_flags): Add support for future processor. (rs6000_option_override_internal): Likewise. (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Add -mfuture. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. * config/rs6000/rs6000.md (cpu attribute): Likewise. * config/rs6000/rs6000.opt (-mfuture): New internal option. --- gcc/config.gcc | 4 ++-- gcc/config/rs6000/aix71.h | 1 + gcc/config/rs6000/aix72.h | 1 + gcc/config/rs6000/aix73.h | 1 + gcc/config/rs6000/driver-rs6000.cc | 2 ++ gcc/config/rs6000/rs6000-c.cc | 2 ++ gcc/config/rs6000/rs6000-cpus.def | 5 +++++ gcc/config/rs6000/rs6000-opts.h | 1 + gcc/config/rs6000/rs6000-tables.opt | 11 +++++++---- gcc/config/rs6000/rs6000.cc | 30 +++++++++++++++++++++-------- gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 6 ++++++ 13 files changed, 52 insertions(+), 15 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 9b616bd6e1f..d45d1faba7a 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -541,7 +541,7 @@ powerpc*-*-*) extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h" extra_headers="${extra_headers} amo.h" case x$with_cpu in - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500) + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture) cpu_is_64bit=yes ;; esac @@ -5649,7 +5649,7 @@ case "${target}" in tm_defines="${tm_defines} CONFIG_PPC405CR" eval "with_$which=405" ;; - "" | common | native \ + "" | common | native | future \ | power[3456789] | power1[01] | power5+ | power6x \ | powerpc | powerpc64 | powerpc64le \ | rs64 \ diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 4350dcd8952..505986b33d6 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future: -mfuture; \ mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h index fe59f8319b4..242ca94bd06 100644 --- a/gcc/config/rs6000/aix72.h +++ b/gcc/config/rs6000/aix72.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future: -mfuture; \ mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h index 1318b0b3662..2bd6b4bb3c4 100644 --- a/gcc/config/rs6000/aix73.h +++ b/gcc/config/rs6000/aix73.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future: -mfuture; \ mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ diff --git a/gcc/config/rs6000/driver-rs6000.cc b/gcc/config/rs6000/driver-rs6000.cc index a054827b2e0..57199b3172f 100644 --- a/gcc/config/rs6000/driver-rs6000.cc +++ b/gcc/config/rs6000/driver-rs6000.cc @@ -453,6 +453,7 @@ static const struct asm_name asm_names[] = { { "power9", "-mpwr9" }, { "power10", "-mpwr10" }, { "power11", "-mpwr11" }, + { "future", "-mfuture" }, { "powerpc", "-mppc" }, { "rs64", "-mppc" }, { "603", "-m603" }, @@ -482,6 +483,7 @@ static const struct asm_name asm_names[] = { { "power9", "-mpower9" }, { "power10", "-mpower10" }, { "power11", "-mpower11" }, + { "future", "-mfuture" }, { "a2", "-ma2" }, { "powerpc", "-mppc" }, { "powerpc64", "-mppc64" }, diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 4dc80e598fa..b0b5701c7fa 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -438,6 +438,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); if ((flags & OPTION_MASK_POWER11) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11"); + if ((flags & OPTION_MASK_FUTURE) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_FUTURE"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 84fac8bdac1..e2e7c5ff191 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -89,6 +89,9 @@ #define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \ | OPTION_MASK_POWER11) +#define FUTURE_MASKS_SERVER (POWER11_MASKS_SERVER \ + | OPTION_MASK_FUTURE) + /* Flags that need to be turned off if -mno-vsx. */ #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_KEYWORD \ @@ -125,6 +128,7 @@ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_FLOAT128_KEYWORD \ | OPTION_MASK_FPRND \ + | OPTION_MASK_FUTURE \ | OPTION_MASK_POWER10 \ | OPTION_MASK_POWER11 \ | OPTION_MASK_P10_FUSION \ @@ -255,6 +259,7 @@ RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | POWER11_MASKS_SERVER) +RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | FUTURE_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 88e357835a5..c25ddf92858 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -63,6 +63,7 @@ enum processor_type PROCESSOR_POWER9, PROCESSOR_POWER10, PROCESSOR_POWER11, + PROCESSOR_FUTURE, PROCESSOR_RS64A, PROCESSOR_MPCCORE, diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index a5649fef1ec..fc187c641f8 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -189,14 +189,17 @@ EnumValue Enum(rs6000_cpu_opt_value) String(power11) Value(53) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc) Value(54) +Enum(rs6000_cpu_opt_value) String(future) Value(54) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc64) Value(55) +Enum(rs6000_cpu_opt_value) String(powerpc) Value(55) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(56) +Enum(rs6000_cpu_opt_value) String(powerpc64) Value(56) EnumValue -Enum(rs6000_cpu_opt_value) String(rs64) Value(57) +Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(57) + +EnumValue +Enum(rs6000_cpu_opt_value) String(rs64) Value(58) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 2b185165610..19086c59afe 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1068,7 +1068,7 @@ struct processor_costs power9_cost = { COSTS_N_INSNS (3), /* SF->DF convert */ }; -/* Instruction costs on Power10/Power11 processors. */ +/* Instruction costs on Power10/Power11/future processors. */ static const struct processor_costs power10_cost = { COSTS_N_INSNS (2), /* mulsi */ @@ -4388,7 +4388,8 @@ rs6000_option_override_internal (bool global_init_p) if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION)) { if (rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE) rs6000_isa_flags |= OPTION_MASK_P10_FUSION; else rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION; @@ -4418,6 +4419,7 @@ rs6000_option_override_internal (bool global_init_p) && rs6000_tune != PROCESSOR_POWER9 && rs6000_tune != PROCESSOR_POWER10 && rs6000_tune != PROCESSOR_POWER11 + && rs6000_tune != PROCESSOR_FUTURE && rs6000_tune != PROCESSOR_PPCA2 && rs6000_tune != PROCESSOR_CELL && rs6000_tune != PROCESSOR_PPC476); @@ -4433,6 +4435,7 @@ rs6000_option_override_internal (bool global_init_p) || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_PPCE500MC || rs6000_tune == PROCESSOR_PPCE500MC64 || rs6000_tune == PROCESSOR_PPCE5500 @@ -4733,6 +4736,7 @@ rs6000_option_override_internal (bool global_init_p) case PROCESSOR_POWER10: case PROCESSOR_POWER11: + case PROCESSOR_FUTURE: rs6000_cost = &power10_cost; break; @@ -5905,6 +5909,8 @@ rs6000_machine_from_flags (void) flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL | OPTION_MASK_ALTIVEC); + if ((flags & (FUTURE_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0) + return "future"; if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0) return "power11"; if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) @@ -10156,6 +10162,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, case PROCESSOR_POWER9: case PROCESSOR_POWER10: case PROCESSOR_POWER11: + case PROCESSOR_FUTURE: if (DECIMAL_FLOAT_MODE_P (mode)) return 1; if (VECTOR_MODE_P (mode)) @@ -18243,7 +18250,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, /* Separate a load from a narrower, dependent store. */ if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE) && GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (dep_insn)) == SET && MEM_P (XEXP (PATTERN (insn), 1)) @@ -18283,6 +18291,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) @@ -18858,6 +18867,7 @@ rs6000_issue_rate (void) return 6; case PROCESSOR_POWER10: case PROCESSOR_POWER11: + case PROCESSOR_FUTURE: return 8; default: return 1; @@ -19573,10 +19583,11 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose, if (rs6000_tune == PROCESSOR_POWER6) load_store_pendulum = 0; - /* Do Power10/Power11 dependent reordering. */ + /* Do Power10/Power11/future dependent reordering. */ if (last_scheduled_insn && (rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11)) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE)) power10_sched_reorder (ready, n_ready - 1); return rs6000_issue_rate (); @@ -19600,10 +19611,11 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready, && recog_memoized (last_scheduled_insn) >= 0) return power9_sched_reorder2 (ready, *pn_ready - 1); - /* Do Power10/Power11 dependent reordering. */ + /* Do Power10/Power11/future dependent reordering. */ if (last_scheduled_insn && (rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11)) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE)) return power10_sched_reorder (ready, *pn_ready - 1); return cached_can_issue_more; @@ -22821,7 +22833,8 @@ rs6000_register_move_cost (machine_mode mode, out to be a nop. */ if (rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE) ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode); else ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode); @@ -24491,6 +24504,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true }, { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, + { "future", OPTION_MASK_FUTURE, false, false }, { "power10", OPTION_MASK_POWER10, false, true }, { "power11", OPTION_MASK_POWER11, false, false }, { "hard-dfp", OPTION_MASK_DFP, false, true }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 3d55e078df0..daf1a1d41e8 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -101,6 +101,7 @@ you make changes here, make them also there. */ #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future: -mfuture; \ mcpu=power11: -mpower11; \ mcpu=power10: -mpower10; \ mcpu=power9: -mpower9; \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 0479c062dba..d266f93ff2e 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -364,7 +364,7 @@ (define_attr "cpu" ppc750,ppc7400,ppc7450, ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, - power4,power5,power6,power7,power8,power9,power10,power11, + power4,power5,power6,power7,power8,power9,power10,power11,future, rs64a,mpccore,cell,ppca2,titan" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 94323bd1db2..876b9f0d4af 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -630,6 +630,12 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. +;; Users should not use -mfuture, but we need to use a bit to identify when +;; the user changes the default cpu via #pragma GCC target("cpu=future") +;; and then resets it later. +mfuture +Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) WarnRemoved + ; Documented parameters -param=rs6000-vect-unroll-limit=