diff mbox series

[V4,5/5] Change TARGET_MODULO to TARGET_POWER9.

Message ID ZzhS82aSnHC9LkFc@cowardly-lion.the-meissners.org
State New
Headers show
Series Add more user friendly TARGET_ names for PowerPC | expand

Commit Message

Michael Meissner Nov. 16, 2024, 8:08 a.m. UTC 
This patch changes TARGET_MODULO to TARGET_POWER9.  The -mmodulo switch is not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 3.0 (Power9).

I have built GCC for both big and little endian systems and there were no
regressions.  Can I check this patch into GCC 15?

2024-11-15  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* gcc/config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported):
	Change TARGET_MODULO to TARGET_POWER9.
	* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
	Likewise.
	* gcc/config/rs6000/rs6000.h (TARGET_CTZ): Likewise.
	(TARGET_EXTSWSLI): Likewise.
	(TARGET_MADDLD): Likewise.
	(TARGET_POWER9): New macro.
	* gcc/config/rs6000/rs6000.md (enabled attribute): Change TARGET_MODULO
	to TARGET_POWER9.
	(mod<mode>3): Likewise.
	(umod<mode>3): Likewise.
	(divide/modulo peephole2): Likewise.
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.cc         |  4 ++--
 gcc/config/rs6000/rs6000.h          |  7 ++++---
 gcc/config/rs6000/rs6000.md         | 14 +++++++-------
 4 files changed, 15 insertions(+), 14 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index dae43b672ea..b6093b3cb64 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -169,9 +169,9 @@  rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode)
     case ENB_P8V:
       return TARGET_P8_VECTOR;
     case ENB_P9:
-      return TARGET_MODULO;
+      return TARGET_POWER9;
     case ENB_P9_64:
-      return TARGET_MODULO && TARGET_POWERPC64;
+      return TARGET_POWER9 && TARGET_POWERPC64;
     case ENB_P9V:
       return TARGET_P9_VECTOR;
     case ENB_P10:
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 2683fff80cf..2b185165610 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3886,7 +3886,7 @@  rs6000_option_override_internal (bool global_init_p)
 
   /* For the newer switches (vsx, dfp, etc.) set some of the older options,
      unless the user explicitly used the -mno-<option> to disable the code.  */
-  if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
+  if (TARGET_P9_VECTOR || TARGET_POWER9 || TARGET_P9_MISC)
     rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_P9_MINMAX)
     {
@@ -22416,7 +22416,7 @@  rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
 	    *total = rs6000_cost->divsi;
 	}
       /* Add in shift and subtract for MOD unless we have a mod instruction. */
-      if ((!TARGET_MODULO
+      if ((!TARGET_POWER9
 	   || (RS6000_DISABLE_SCALAR_MODULO && SCALAR_INT_MODE_P (mode)))
 	 && (code == MOD || code == UMOD))
 	*total += COSTS_N_INSNS (2);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 94853e11fc8..3d55e078df0 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -463,9 +463,9 @@  extern int rs6000_vector_align[];
 #define TARGET_FCTIWUZ	TARGET_POWER7
 /* Only powerpc64 and powerpc476 support fctid.  */
 #define TARGET_FCTID	(TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
-#define TARGET_CTZ	TARGET_MODULO
-#define TARGET_EXTSWSLI	(TARGET_MODULO && TARGET_POWERPC64)
-#define TARGET_MADDLD	TARGET_MODULO
+#define TARGET_CTZ	TARGET_POWER9
+#define TARGET_EXTSWSLI	(TARGET_POWER9 && TARGET_POWERPC64)
+#define TARGET_MADDLD	TARGET_POWER9
 
 /* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that.  */
 #define TARGET_DIRECT_MOVE	TARGET_P8_VECTOR
@@ -506,6 +506,7 @@  extern int rs6000_vector_align[];
 #define TARGET_POWER5X		TARGET_FPRND
 #define TARGET_POWER6		TARGET_CMPB
 #define TARGET_POWER7		TARGET_POPCNTD
+#define TARGET_POWER9		TARGET_MODULO
 
 /* In switching from using target_flags to using rs6000_isa_flags, the options
    machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>.  The MASK_<xxxx>
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b88254bb6ae..0479c062dba 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -403,7 +403,7 @@  (define_attr "enabled" ""
      (const_int 1)
 
      (and (eq_attr "isa" "p9")
-	  (match_test "TARGET_MODULO"))
+	  (match_test "TARGET_POWER9"))
      (const_int 1)
 
      (and (eq_attr "isa" "p9v")
@@ -3457,7 +3457,7 @@  (define_expand "mod<mode>3"
       || INTVAL (operands[2]) <= 0
       || (i = exact_log2 (INTVAL (operands[2]))) < 0)
     {
-      if (!TARGET_MODULO)
+      if (!TARGET_POWER9)
 	FAIL;
 
       operands[2] = force_reg (<MODE>mode, operands[2]);
@@ -3491,7 +3491,7 @@  (define_insn "*mod<mode>3"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r")
         (mod:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
 		 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
-  "TARGET_MODULO && !RS6000_DISABLE_SCALAR_MODULO"
+  "TARGET_POWER9 && !RS6000_DISABLE_SCALAR_MODULO"
   "mods<wd> %0,%1,%2"
   [(set_attr "type" "div")
    (set_attr "size" "<bits>")])
@@ -3502,7 +3502,7 @@  (define_expand "umod<mode>3"
   [(set (match_operand:GPR 0 "gpc_reg_operand")
 	(umod:GPR (match_operand:GPR 1 "gpc_reg_operand")
 		  (match_operand:GPR 2 "gpc_reg_operand")))]
-  "TARGET_MODULO"
+  "TARGET_POWER9"
 {
   if (RS6000_DISABLE_SCALAR_MODULO)
     {
@@ -3520,7 +3520,7 @@  (define_insn "*umod<mode>3"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r,r")
         (umod:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
 		  (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
-  "TARGET_MODULO && !RS6000_DISABLE_SCALAR_MODULO"
+  "TARGET_POWER9 && !RS6000_DISABLE_SCALAR_MODULO"
   "modu<wd> %0,%1,%2"
   [(set_attr "type" "div")
    (set_attr "size" "<bits>")])
@@ -3536,7 +3536,7 @@  (define_peephole2
    (set (match_operand:GPR 3 "gpc_reg_operand")
 	(mod:GPR (match_dup 1)
 		 (match_dup 2)))]
-  "TARGET_MODULO
+  "TARGET_POWER9
    && ! reg_mentioned_p (operands[0], operands[1])
    && ! reg_mentioned_p (operands[0], operands[2])
    && ! reg_mentioned_p (operands[3], operands[1])
@@ -3558,7 +3558,7 @@  (define_peephole2
    (set (match_operand:GPR 3 "gpc_reg_operand")
 	(umod:GPR (match_dup 1)
 		  (match_dup 2)))]
-  "TARGET_MODULO
+  "TARGET_POWER9
    && ! reg_mentioned_p (operands[0], operands[1])
    && ! reg_mentioned_p (operands[0], operands[2])
    && ! reg_mentioned_p (operands[3], operands[1])