From patchwork Sat Nov 16 08:02:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 2012300 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=sjzBiyHm; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Xr5xQ0xLGz1xy5 for ; Sat, 16 Nov 2024 19:03:38 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2B0573857C6D for ; Sat, 16 Nov 2024 08:03:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2B0573857C6D Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=sjzBiyHm X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 8A44B3857C68 for ; Sat, 16 Nov 2024 08:03:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8A44B3857C68 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8A44B3857C68 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1731744182; cv=none; b=PI6O/ebs+wvH9cMZPUCyT8pC5ooZx2qqJvd+Ioza196dLZ1kt5GeBOKIDZJg6ahQriKh3uy1TQtwjZMqIdQr3VbHzO8EsDI9zon2lrPVYYu/M4AP/pFKtRhrt16WK2aGEFsxhFZy0YyyKjzypBd2cVzL3ZYgrsfzP2xBBFCtALk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1731744182; c=relaxed/simple; bh=LasKEdqvfLrSH9FC40BgkaWxnynPZQv6CLeqv2kF8bM=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=DiOtY5SGWmir6i+/jjEBwxvuYUfik13TQaB0I3wbntAKufjsPpt5HHr6z8jvhA+dDOYVl2R96esw5vkeSXzSO8qibGkUtiedf/HlFB5tEUoniJCFKt+E+Q9MlFGq2qQeoR9bF5PSu5sAeUJP9hhcE17CSaiwgVrygHP0ka0u/0g= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8A44B3857C68 Received: from pps.filterd (m0353729.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AG6H4J7027043; Sat, 16 Nov 2024 08:03:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h= content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=pp1; bh=I6buoX9YVn06sONKFGud91QRUOX6Xp /OWEOaYoSlopo=; b=sjzBiyHmMJwgYvPdAJO1OxW6iaBoc3UPMo7LxYrkDje657 PQroj50phDqnZwW9uOL5MbpwJgOEhyy8C66KwzHNFfVwwKGvWsNV1c2NLmEmYtLu 0V5J325YLOxQcQqa7rfp3dgQwnjRof1f5mOz9qOoIX2AfsUpB87KCfRdQsYHvTE7 x4i+9XX8IMee5FVwGDO0QAAlD5aZvUppcsvsUEgRSB1vMyv/2UcXb2M8dr6QgY+M It0S4JNMBCeGcFTTm9lv3pd7efPrEXL6GpcMWvgws5UyP/qiX1ydBX6ErUQ29Sjp pN61SbpVJFFEcfalFIXh6IFULdJTV8x5pmYqsZfQ== Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 42xk2vgphf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 16 Nov 2024 08:03:01 +0000 (GMT) Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 4AG7e2Zw029698; Sat, 16 Nov 2024 08:03:00 GMT Received: from smtprelay03.wdc07v.mail.ibm.com ([172.16.1.70]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 42tkjn26b7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 16 Nov 2024 08:03:00 +0000 Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay03.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 4AG82w1X66978098 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 16 Nov 2024 08:02:58 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7C95858051; Sat, 16 Nov 2024 08:02:58 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 272445805E; Sat, 16 Nov 2024 08:02:58 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.98.188]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTPS; Sat, 16 Nov 2024 08:02:58 +0000 (GMT) Date: Sat, 16 Nov 2024 03:02:56 -0500 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner Subject: [PATCH V4 2/5] Change TARGET_FPRND to TARGET_POWER5X. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: fNFpzD4IunuX6OmWgj0EuHKMYXPd20ZG X-Proofpoint-GUID: fNFpzD4IunuX6OmWgj0EuHKMYXPd20ZG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 phishscore=0 clxscore=1015 suspectscore=0 spamscore=0 impostorscore=0 bulkscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160066 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch changes TARGET_POWER5X to TARGET_POWER5. The -mfprnd switch is not being changed, just the name of the macros used to determine if the PowerPC processor supports ISA 2.4 (Power5x). I have GCC with this patch on both big and little endian systems and there were no regressions. Can I check this patch into GCC 15? 2024-11-15 Michael Meissner gcc/ * gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal): Change TARGET_FPRND to TARGET_POWER5X. * gcc/config/rs6000/rs6000.h (TARGET_POWERP5X): New macro. * gcc/config/rs6000/rs6000.md (fmod3): Change TARGET_FPRND to TARGET_POWER5X. (remainder3): Likewise. (fctiwuz_): Likewise. (ceil2): Likewise. (floor2): Likewise. (round2): Likewise. --- gcc/config/rs6000/rs6000.cc | 4 ++-- gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.md | 14 +++++++------- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 84b23f58d85..8dfaea5df07 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3922,7 +3922,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks); else if (TARGET_CMPB) rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks); - else if (TARGET_FPRND) + else if (TARGET_POWER5X) rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks); else if (TARGET_POWER5) rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks); @@ -3949,7 +3949,7 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_CRYPTO; } - if (!TARGET_FPRND && TARGET_VSX) + if (!TARGET_POWER5X && TARGET_VSX) { if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND) /* TARGET_VSX = 1 implies Power 7 and newer */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 80d954e1178..8573b859405 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -503,6 +503,7 @@ extern int rs6000_vector_align[]; /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5. */ #define TARGET_POWER5 TARGET_POPCNTB +#define TARGET_POWER5X TARGET_FPRND /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9c7e92d5fe2..e7c532fbaa0 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5171,7 +5171,7 @@ (define_expand "fmod3" (use (match_operand:SFDF 1 "gpc_reg_operand")) (use (match_operand:SFDF 2 "gpc_reg_operand"))] "TARGET_HARD_FLOAT - && TARGET_FPRND + && TARGET_POWER5X && flag_unsafe_math_optimizations" { rtx div = gen_reg_rtx (mode); @@ -5189,7 +5189,7 @@ (define_expand "remainder3" (use (match_operand:SFDF 1 "gpc_reg_operand")) (use (match_operand:SFDF 2 "gpc_reg_operand"))] "TARGET_HARD_FLOAT - && TARGET_FPRND + && TARGET_POWER5X && flag_unsafe_math_optimizations" { rtx div = gen_reg_rtx (mode); @@ -6687,7 +6687,7 @@ (define_insn "fctiwuz_" (define_insn "*friz" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa") (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))] - "TARGET_HARD_FLOAT && TARGET_FPRND + "TARGET_HARD_FLOAT && TARGET_POWER5X && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ" "@ friz %0,%1 @@ -6815,7 +6815,7 @@ (define_insn "btrunc2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIZ))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ friz %0,%1 xsrdpiz %x0,%x1" @@ -6825,7 +6825,7 @@ (define_insn "ceil2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIP))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ frip %0,%1 xsrdpip %x0,%x1" @@ -6835,7 +6835,7 @@ (define_insn "floor2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIM))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ frim %0,%1 xsrdpim %x0,%x1" @@ -6846,7 +6846,7 @@ (define_insn "round2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FRIN))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "frin %0,%1" [(set_attr "type" "fp")])