diff mbox series

[V4,2/5] Change TARGET_FPRND to TARGET_POWER5X.

Message ID ZzhRsLKF6JbbkbcW@cowardly-lion.the-meissners.org
State New
Headers show
Series Add more user friendly TARGET_ names for PowerPC | expand

Commit Message

Michael Meissner Nov. 16, 2024, 8:02 a.m. UTC 
This patch changes TARGET_POWER5X to TARGET_POWER5.  The -mfprnd switch is not
being changed, just the name of the macros used to determine if the PowerPC
processor supports ISA 2.4 (Power5x).

I have GCC with this patch on both big and little endian systems and there were
no regressions.  Can I check this patch into GCC 15?

2024-11-15  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* gcc/config/rs6000/rs6000.cc (rs6000_option_override_internal):
	Change TARGET_FPRND to TARGET_POWER5X.
	* gcc/config/rs6000/rs6000.h (TARGET_POWERP5X): New macro.
	* gcc/config/rs6000/rs6000.md (fmod<mode>3): Change TARGET_FPRND to
	TARGET_POWER5X.
	(remainder<mode>3): Likewise.
	(fctiwuz_<mode): Likewise.
	(btrunc<mode>): Likewise.
	(ceil<mode>2): Likewise.
	(floor<mode>2): Likewise.
	(round<mode>2): Likewise.
---
 gcc/config/rs6000/rs6000.cc |  4 ++--
 gcc/config/rs6000/rs6000.h  |  1 +
 gcc/config/rs6000/rs6000.md | 14 +++++++-------
 3 files changed, 10 insertions(+), 9 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 84b23f58d85..8dfaea5df07 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3922,7 +3922,7 @@  rs6000_option_override_internal (bool global_init_p)
     rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
   else if (TARGET_CMPB)
     rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
-  else if (TARGET_FPRND)
+  else if (TARGET_POWER5X)
     rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
   else if (TARGET_POWER5)
     rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
@@ -3949,7 +3949,7 @@  rs6000_option_override_internal (bool global_init_p)
       rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
     }
 
-  if (!TARGET_FPRND && TARGET_VSX)
+  if (!TARGET_POWER5X && TARGET_VSX)
     {
       if (rs6000_isa_flags_explicit & OPTION_MASK_FPRND)
 	/* TARGET_VSX = 1 implies Power 7 and newer */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 80d954e1178..8573b859405 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -503,6 +503,7 @@  extern int rs6000_vector_align[];
 
 /* Convert ISA bits like POPCNTB to PowerPC processors like POWER5.  */
 #define TARGET_POWER5		TARGET_POPCNTB
+#define TARGET_POWER5X		TARGET_FPRND
 
 /* In switching from using target_flags to using rs6000_isa_flags, the options
    machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>.  The MASK_<xxxx>
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9c7e92d5fe2..e7c532fbaa0 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5171,7 +5171,7 @@  (define_expand "fmod<mode>3"
 	(use (match_operand:SFDF 1 "gpc_reg_operand"))
 	(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
    && flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (<MODE>mode);
@@ -5189,7 +5189,7 @@  (define_expand "remainder<mode>3"
 	(use (match_operand:SFDF 1 "gpc_reg_operand"))
 	(use (match_operand:SFDF 2 "gpc_reg_operand"))]
   "TARGET_HARD_FLOAT
-   && TARGET_FPRND
+   && TARGET_POWER5X
    && flag_unsafe_math_optimizations"
 {
   rtx div = gen_reg_rtx (<MODE>mode);
@@ -6687,7 +6687,7 @@  (define_insn "fctiwuz_<mode>"
 (define_insn "*friz"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
 	(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND
+  "TARGET_HARD_FLOAT && TARGET_POWER5X
    && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
   "@
    friz %0,%1
@@ -6815,7 +6815,7 @@  (define_insn "btrunc<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIZ))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
    friz %0,%1
    xsrdpiz %x0,%x1"
@@ -6825,7 +6825,7 @@  (define_insn "ceil<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIP))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
    frip %0,%1
    xsrdpip %x0,%x1"
@@ -6835,7 +6835,7 @@  (define_insn "floor<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
 		     UNSPEC_FRIM))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "@
    frim %0,%1
    xsrdpim %x0,%x1"
@@ -6846,7 +6846,7 @@  (define_insn "round<mode>2"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
 	(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
 		     UNSPEC_FRIN))]
-  "TARGET_HARD_FLOAT && TARGET_FPRND"
+  "TARGET_HARD_FLOAT && TARGET_POWER5X"
   "frin %0,%1"
   [(set_attr "type" "fp")])