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Wed, 13 Nov 2024 19:47:35 +0000 Received: from smtpav02.dal12v.mail.ibm.com (smtpav02.dal12v.mail.ibm.com [10.241.53.101]) by smtprelay02.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 4ADJlY5o55050684 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 13 Nov 2024 19:47:34 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 331B95805A; Wed, 13 Nov 2024 19:47:34 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D65C858051; Wed, 13 Nov 2024 19:47:33 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.109.186]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTPS; Wed, 13 Nov 2024 19:47:33 +0000 (GMT) Date: Wed, 13 Nov 2024 14:47:32 -0500 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner Subject: [PATCH V3, 05/11] Change TARGET_FPRND to TARGET_POWER5X Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: FwYeY9gVSuEQBDLS2EKUC3J64CN32UCX X-Proofpoint-GUID: FwYeY9gVSuEQBDLS2EKUC3J64CN32UCX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 adultscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411130161 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org As part of the architecture flags patches, this patch changes the use of TARGET_FPRND to TARGET_POWER5X. The FPRND instruction was added in power5+. I have built both big endian and little endian bootstrap compilers and there were no regressions. In addition, I constructed a test case that used every archiecture define (like _ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran this test for all supported combinations of -mcpu, big/little endian, and 32/64 bit support. Every single instance generated exactly the same code with the patches installed compared to the compiler before installing the patches. Can I install this patch on the GCC 15 trunk? 2024-11-13 Michael Meissner * config/rs6000/rs6000.cc (report_architecture_mismatch): Use TARGET_POWER5X instead of TARGET_FPRND. * config/rs6000/rs6000.md (fmod3): Use TARGET_POWER5X instead of TARGET_FPRND. (remainder3): Likewise. (fctiwuz_): Likewise. (btrunc2): Likewise. (ceil2): Likewise. (floor2): Likewise. (round): Likewise. --- gcc/config/rs6000/rs6000.cc | 2 +- gcc/config/rs6000/rs6000.md | 14 +++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index eadd55ed5bb..e1aef318087 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -25428,7 +25428,7 @@ report_architecture_mismatch (void) rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks); else if (TARGET_CMPB) rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks); - else if (TARGET_FPRND) + else if (TARGET_POWER5X) rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks); else if (TARGET_POPCNTB) rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 10d13bf812d..7f9fe609a03 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5171,7 +5171,7 @@ (define_expand "fmod3" (use (match_operand:SFDF 1 "gpc_reg_operand")) (use (match_operand:SFDF 2 "gpc_reg_operand"))] "TARGET_HARD_FLOAT - && TARGET_FPRND + && TARGET_POWER5X && flag_unsafe_math_optimizations" { rtx div = gen_reg_rtx (mode); @@ -5189,7 +5189,7 @@ (define_expand "remainder3" (use (match_operand:SFDF 1 "gpc_reg_operand")) (use (match_operand:SFDF 2 "gpc_reg_operand"))] "TARGET_HARD_FLOAT - && TARGET_FPRND + && TARGET_POWER5X && flag_unsafe_math_optimizations" { rtx div = gen_reg_rtx (mode); @@ -6687,7 +6687,7 @@ (define_insn "fctiwuz_" (define_insn "*friz" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa") (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))] - "TARGET_HARD_FLOAT && TARGET_FPRND + "TARGET_HARD_FLOAT && TARGET_POWER5X && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ" "@ friz %0,%1 @@ -6815,7 +6815,7 @@ (define_insn "btrunc2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIZ))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ friz %0,%1 xsrdpiz %x0,%x1" @@ -6825,7 +6825,7 @@ (define_insn "ceil2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIP))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ frip %0,%1 xsrdpip %x0,%x1" @@ -6835,7 +6835,7 @@ (define_insn "floor2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRIM))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "@ frim %0,%1 xsrdpim %x0,%x1" @@ -6846,7 +6846,7 @@ (define_insn "round2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FRIN))] - "TARGET_HARD_FLOAT && TARGET_FPRND" + "TARGET_HARD_FLOAT && TARGET_POWER5X" "frin %0,%1" [(set_attr "type" "fp")])