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Fri, 25 Oct 2024 19:50:40 +0000 (GMT) Date: Fri, 25 Oct 2024 15:50:39 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , Peter Bergner Subject: [PATCH 9/11] Update tests to work with architecture flags changes. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: XbYVu56Qi7xl3bKEQ9JLtBlGX0WrWYNk X-Proofpoint-GUID: XbYVu56Qi7xl3bKEQ9JLtBlGX0WrWYNk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 adultscore=0 mlxlogscore=905 clxscore=1015 impostorscore=0 mlxscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410250148 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Two tests used -mvsx to raise the processor level to at least power7. These tests were rewritten to add cpu=power7 support. I have built both big endian and little endian bootstrap compilers and there were no regressions. In addition, I constructed a test case that used every archiecture define (like _ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran this test for all supported combinations of -mcpu, big/little endian, and 32/64 bit support. Every single instance generated exactly the same code with the patches installed compared to the compiler before installing the patches. Can I install this patch on the GCC 15 trunk? 2024-10-25 Michael Meissner gcc/testsuite/ * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7 when we need to add VSX support. Add test for adding cpu=power7 no-vsx to generate only Altivec instructions. * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX instructions. --- .../gcc.target/powerpc/ppc-target-4.c | 38 ++++++++++++++----- gcc/testsuite/gcc.target/powerpc/pr115688.c | 3 +- 2 files changed, 31 insertions(+), 10 deletions(-) diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c index feef76db461..5e2ecf34f24 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c @@ -2,7 +2,7 @@ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_fprs } */ /* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec -mabi=altivec -fno-unroll-loops" } */ -/* { dg-final { scan-assembler-times "vaddfp" 1 } } */ +/* { dg-final { scan-assembler-times "vaddfp" 2 } } */ /* { dg-final { scan-assembler-times "xvaddsp" 1 } } */ /* { dg-final { scan-assembler-times "fadds" 1 } } */ @@ -18,10 +18,6 @@ #error "__VSX__ should not be defined." #endif -#pragma GCC target("altivec,vsx") -#include -#pragma GCC reset_options - #pragma GCC push_options #pragma GCC target("altivec,no-vsx") @@ -33,6 +29,7 @@ #error "__VSX__ should not be defined." #endif +/* Altivec build, generate vaddfp. */ void av_add (vector float *a, vector float *b, vector float *c) { @@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c) unsigned long n = SIZE / 4; for (i = 0; i < n; i++) - a[i] = vec_add (b[i], c[i]); + a[i] = b[i] + c[i]; } -#pragma GCC target("vsx") +/* cpu=power7 must be used to enable VSX. */ +#pragma GCC target("cpu=power7,vsx") #ifndef __ALTIVEC__ #error "__ALTIVEC__ should be defined." @@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c) #error "__VSX__ should be defined." #endif +/* VSX build on power7, generate xsaddsp. */ void vsx_add (vector float *a, vector float *b, vector float *c) { @@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c) unsigned long n = SIZE / 4; for (i = 0; i < n; i++) - a[i] = vec_add (b[i], c[i]); + a[i] = b[i] + c[i]; +} + +#pragma GCC target("cpu=power7,no-vsx") + +#ifndef __ALTIVEC__ +#error "__ALTIVEC__ should be defined." +#endif + +#ifdef __VSX__ +#error "__VSX__ should not be defined." +#endif + +/* Altivec build on power7 with no VSX, generate vaddfp. */ +void +av2_add (vector float *a, vector float *b, vector float *c) +{ + unsigned long i; + unsigned long n = SIZE / 4; + + for (i = 0; i < n; i++) + a[i] = b[i] + c[i]; } #pragma GCC pop_options -#pragma GCC target("no-vsx,no-altivec") #ifdef __ALTIVEC__ #error "__ALTIVEC__ should not be defined." @@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c) #error "__VSX__ should not be defined." #endif +/* Default power5 build, generate scalar fadds. */ void norm_add (float *a, float *b, float *c) { diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c b/gcc/testsuite/gcc.target/powerpc/pr115688.c index 5222e66ef17..00c7c301436 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr115688.c +++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c @@ -7,7 +7,8 @@ /* Verify there is no ICE under 32 bit env. */ -__attribute__((target("vsx"))) +/* cpu=power7 must be used to enable VSX. */ +__attribute__((target("cpu=power7,vsx"))) int test (void) { return 0;