From patchwork Sun Oct 6 19:26:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 1993299 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XMC3B53h8z1xtV for ; Mon, 7 Oct 2024 06:27:16 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 69616386074B for ; Sun, 6 Oct 2024 19:27:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from dellerweb.de (unknown [IPv6:2a02:c207:3003:236::1]) by sourceware.org (Postfix) with ESMTPS id 9C3053858D20 for ; Sun, 6 Oct 2024 19:26:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9C3053858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=parisc-linux.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=parisc-linux.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9C3053858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a02:c207:3003:236::1 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1728242811; cv=none; b=Yb8u9MZ9glmnqo/pSAgLxW5XBy+xs7lpD87XJIGrig/rK7n/NIcOpkjGut5VaUx/WMm2rKKEIBnxnjHjjMmDFa1Rna0ZmiRvX7w6wQGRwTH7A3l0F8cH2NFCQmgY0bx1rxrkFOUf6L6VgQEgmqKPi1OPH7GFOMRLAMFG9Tjkur4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1728242811; c=relaxed/simple; bh=TXJ3Ys2jMrbuiu1LzQolFZ23WaFsTxjkgflJieVtVGQ=; h=Date:From:To:Subject:Message-ID:MIME-Version; b=YicqMKkAmkY9yhngF1wK6owSOK4rSIW1wCGFyRQ3WOJClTmGBTLxXudUcEUO5RRsOAWL2Kv2s1B1hlPQWuzaGSJI9DnSgpcYyQYVW+GncGSxMrMce47S0gLPzNPja0EQ06PpeMIWUKc8sKykq/xuDk6GAXLS3jqSAZ4jmYJyyIw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mx3210.localdomain (bras-base-otwaon0906w-grc-03-142-126-114-136.dsl.bell.ca [142.126.114.136]) by dellerweb.de (Postfix) with ESMTPSA id 13B131600213; Sun, 6 Oct 2024 21:26:33 +0200 (CEST) Received: by mx3210.localdomain (Postfix, from userid 1000) id 1E4EDD6027A; Sun, 6 Oct 2024 15:26:30 -0400 (EDT) Date: Sun, 6 Oct 2024 15:26:30 -0400 From: John David Anglin To: GCC Patches Subject: [committed] hppa: Use stack slot SP-40 to copy between integer and floating-point registers Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP, URIBL_DBL_SPAM autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Tested on hppa64-hp-hpux11.11 and hppa-unknown-linux-gnu. Committed to trunk. Dave --- hppa: Use stack slot SP-40 to copy between integer and floating-point registers 2024-10-06 John David Anglin gcc/ChangeLog: * config/pa/pa-64.h (PA_SECONDARY_MEMORY_NEEDED): Define to false. Update comment. * config/pa/pa.md: Modify 64-bit move patterns to support copying between integer and floating-point registers using stack slot SP-40. diff --git a/gcc/config/pa/pa-64.h b/gcc/config/pa/pa-64.h index b676468d2ce..3fae3f851e5 100644 --- a/gcc/config/pa/pa-64.h +++ b/gcc/config/pa/pa-64.h @@ -91,9 +91,9 @@ along with GCC; see the file COPYING3. If not see the RTL to avoid scheduling related problems. For example, the store and load could be separated by a call to a pure or const function which has no frame and this function might also use SP-16. - We have 14-bit immediates on the 64-bit port, so we use secondary - memory for the copies. */ -#define PA_SECONDARY_MEMORY_NEEDED(MODE, CLASS1, CLASS2) \ - (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \ - || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1)) - + + On the 64-bit port, I couldn't get SECONDARY_MEMORY_NEEDED to work + with LRA, so I modified the move patterns to use SP-40. The HP + compiler also uses this slot in the frame marker for moving data + between the general and floating-point registers. */ +#define PA_SECONDARY_MEMORY_NEEDED(MODE, CLASS1, CLASS2) false diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index f0520bb2c35..bf59b7f601e 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2222,9 +2222,9 @@ (define_insn "" [(set (match_operand:SI 0 "move_dest_operand" - "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T") + "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f") (match_operand:SI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))] + "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))] "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && !TARGET_SOFT_FLOAT @@ -2241,10 +2241,12 @@ {mfctl|mfctl,w} %%sar,%0 fcpy,sgl %f1,%0 fldw%F1 %1,%0 - fstw%F0 %1,%0" - [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore") + fstw%F0 %1,%0 + fstw %1,-40(%%sp)\n\tldw -40(%%sp),%0 + stw %1,-40(%%sp)\n\tfldw -40(%%sp),%0" + [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")]) (define_insn "" [(set (match_operand:SI 0 "move_dest_operand" @@ -4107,9 +4109,9 @@ (define_insn "" [(set (match_operand:DF 0 "move_dest_operand" - "=!*r,*r,*r,*r,*r,Q,f,f,T") + "=!*r,*r,*r,*r,*r,Q,f,f,T,?*r,?f") (match_operand:DF 1 "move_src_operand" - "!*rG,J,N,K,RQ,*rG,fG,RT,f"))] + "!*rG,J,N,K,RQ,*rG,fG,RT,f,f,*r"))] "(register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode)) && !TARGET_SOFT_FLOAT && TARGET_64BIT" @@ -4122,10 +4124,12 @@ std%M0 %r1,%0 fcpy,dbl %f1,%0 fldd%F1 %1,%0 - fstd%F0 %1,%0" - [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore") + fstd%F0 %1,%0 + fstd %1,-40(%%sp)\n\tldd -40(%%sp),%0 + std %1,-40(%%sp)\n\tfldd -40(%%sp),%0" + [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore,fpstore_load,store_fpload") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")]) (define_insn "" [(set (match_operand:DF 0 "move_dest_operand" @@ -4281,9 +4285,9 @@ (define_insn "" [(set (match_operand:DI 0 "move_dest_operand" - "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T") + "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f") (match_operand:DI 1 "move_src_operand" - "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))] + "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))] "(register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode)) && !TARGET_SOFT_FLOAT && TARGET_64BIT" @@ -4299,10 +4303,12 @@ {mfctl|mfctl,w} %%sar,%0 fcpy,dbl %f1,%0 fldd%F1 %1,%0 - fstd%F0 %1,%0" - [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore") + fstd%F0 %1,%0 + fstd %1,-40(%%sp)\n\tldd -40(%%sp),%0 + std %1,-40(%%sp)\n\tfldd -40(%%sp),%0" + [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")]) (define_insn "" [(set (match_operand:DI 0 "move_dest_operand" @@ -4513,9 +4519,9 @@ (define_insn "" [(set (match_operand:SF 0 "move_dest_operand" - "=f,!*r,f,*r,T,Q") + "=f,!*r,f,*r,T,Q,?*r,?f") (match_operand:SF 1 "reg_or_0_or_mem_operand" - "fG,!*rG,RT,RQ,f,*rG"))] + "fG,!*rG,RT,RQ,f,*rG,f,*r"))] "(register_operand (operands[0], SFmode) || reg_or_0_operand (operands[1], SFmode)) && !TARGET_SOFT_FLOAT @@ -4526,10 +4532,12 @@ fldw%F1 %1,%0 ldw%M1 %1,%0 fstw%F0 %1,%0 - stw%M0 %r1,%0" - [(set_attr "type" "fpalu,move,fpload,load,fpstore,store") + stw%M0 %r1,%0 + fstw %1,-40(%%sp)\n\tldw -40(%%sp),%0 + stw %1,-40(%%sp)\n\tfldw -40(%%sp),%0" + [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,8,8")]) (define_insn "" [(set (match_operand:SF 0 "move_dest_operand"