From patchwork Fri Aug 2 06:21:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 1968169 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=BK9CeCw2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WZwhw0Bw8z1ybX for ; Fri, 2 Aug 2024 16:21:52 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3E5CA385DDF8 for ; Fri, 2 Aug 2024 06:21:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 8E41E385DDDC for ; Fri, 2 Aug 2024 06:21:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8E41E385DDDC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8E41E385DDDC Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722579690; cv=none; b=aq8WbEJYO+KR8zu4Sb54+HuNn2SVODCqxw/7klmed6XrTU4qD2PF8OCj8SPxC7zeH5opGBh8Ra2qnhaD+4Edze1ZzK8PvS74mJT90phoM5DvjHkRRvIJThk7CRW9I7Kf6zKU4KzcmBipXmSXx3njx0py5EH0q7HpTy2PfYAVehk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722579690; c=relaxed/simple; bh=woEjP2bjRsZuI9tax+shUVC4U2hk0QqfgAl4zsIZNL0=; h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version; b=RPT5UiTyEQsdJTcq5NcyM18g+cj9oy9dAdCoG8OyEKVuPDf6J1RYH8XF5Bf4O1Tf8jybzPuGN+rJGwO98bY/DbA1AeaBIuPgNqjwlqEjtbDC/mBXcJ28sySKWqteoBKEP1x/t8NY4OmcZAqstam2kvJKXIYFQYy9dD2PE1UHC+o= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0353727.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4725uHxN001400; Fri, 2 Aug 2024 06:21:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=date :from:to:subject:message-id:references:mime-version:content-type :in-reply-to; s=pp1; bh=l1V2EkHQxu1CuMq1yArTmO4mrLJyevCKLQnUmcBR 4CI=; b=BK9CeCw2pbX/5jdWKIV9RzUM1J1qQpf0qzhX1G8QZ5Abwv1LXDtjiVc6 IcLoY2RI2s6Xpg3Byxky/HHKlWhlxwsGqJ4lIfXuIby9WYonf7+BPTI7aoLt/Xit 2Qom+VBhgjGVuWL439PvhGXARNB7PHwYzB+5Mi0N1sUp9Tecr8rxoOvATRMTTy4k i2lpXt1rRUlHfS0dyYW9Xkc/2TSM2LaVv4rU7AXqaTgdEteb9Je5EGN8A4ho9XwQ vbJR72GEuiXV0eVdvDx6EX6Bjr09H2NeTiwaCZUHp9K3pHLP5atlLDNV7Q0xKLJu 8eo8R67X/ay+Fnpv5REaHqhYTiiNhA== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 40rr17r7kf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 Aug 2024 06:21:27 +0000 (GMT) Received: from m0353727.ppops.net (m0353727.ppops.net [127.0.0.1]) by pps.reinject (8.18.0.8/8.18.0.8) with ESMTP id 4726LQaP016270; Fri, 2 Aug 2024 06:21:26 GMT Received: from ppma13.dal12v.mail.ibm.com (dd.9e.1632.ip4.static.sl-reverse.com [50.22.158.221]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 40rr17r7kc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 Aug 2024 06:21:26 +0000 (GMT) Received: from pps.filterd (ppma13.dal12v.mail.ibm.com [127.0.0.1]) by ppma13.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 4724JXoT003745; Fri, 2 Aug 2024 06:21:25 GMT Received: from smtprelay07.dal12v.mail.ibm.com ([172.16.1.9]) by ppma13.dal12v.mail.ibm.com (PPS) with ESMTPS id 40ndemwjnh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 Aug 2024 06:21:25 +0000 Received: from smtpav05.wdc07v.mail.ibm.com (smtpav05.wdc07v.mail.ibm.com [10.39.53.232]) by smtprelay07.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 4726LMKG34341410 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 2 Aug 2024 06:21:25 GMT Received: from smtpav05.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B7D815806A; Fri, 2 Aug 2024 06:21:22 +0000 (GMT) Received: from smtpav05.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1899F58068; Fri, 2 Aug 2024 06:21:22 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.67.12]) by smtpav05.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Fri, 2 Aug 2024 06:21:21 +0000 (GMT) Date: Fri, 2 Aug 2024 02:21:18 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner Subject: [PATCH 9/9] Update tests to work with architecture flags changes. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: fJo8H9uiXB0cZd76-GC1uRpt_oI53jga X-Proofpoint-ORIG-GUID: uSCkdJVCqDN0ecjS6QMKVn_vSbpUoigi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-02_02,2024-08-01_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 spamscore=0 mlxlogscore=993 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408020039 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Two tests used -mvsx to raise the processor level to at least power7. These tests were rewritten to add cpu=power7 support. I have built both big endian and little endian bootstrap compilers and there were no regressions. In addition, I constructed a test case that used every archiecture define (like _ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran this test for all supported combinations of -mcpu, big/little endian, and 32/64 bit support. Every single instance generated exactly the same code with the patches installed compared to the compiler before installing the patches. Can I install this patch on the GCC 15 trunk? 2024-08-01 Michael Meissner gcc/testsuite/ * gcc.target/powerpc/ppc-target-4.c: Rewrite the test to add cpu=power7 when we need to add VSX support. Add test for adding cpu=power7 no-vsx to generate only Altivec instructions. * gcc.target/powerpc/pr115688.c: Add cpu=power7 when requesting VSX instructions. --- .../gcc.target/powerpc/ppc-target-4.c | 40 ++++++++++++++----- gcc/testsuite/gcc.target/powerpc/pr115688.c | 3 +- 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c index db9ba500e0e..42f5aa354d0 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c @@ -1,8 +1,8 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-O2 -ffast-math -mdejagnu-cpu=power5 -mno-altivec -mabi=altivec -fno-unroll-loops" } */ -/* { dg-final { scan-assembler-times "vaddfp" 1 } } */ +/* { dg-options "-O3 -ffast-math -mdejagnu-cpu=power5 -mno-altivec -mabi=altivec -fno-unroll-loops" } */ +/* { dg-final { scan-assembler-times "vaddfp" 2 } } */ /* { dg-final { scan-assembler-times "xvaddsp" 1 } } */ /* { dg-final { scan-assembler-times "fadds" 1 } } */ @@ -18,10 +18,6 @@ #error "__VSX__ should not be defined." #endif -#pragma GCC target("altivec,vsx") -#include -#pragma GCC reset_options - #pragma GCC push_options #pragma GCC target("altivec,no-vsx") @@ -33,6 +29,7 @@ #error "__VSX__ should not be defined." #endif +/* Altivec build, generate vaddfp. */ void av_add (vector float *a, vector float *b, vector float *c) { @@ -40,10 +37,11 @@ av_add (vector float *a, vector float *b, vector float *c) unsigned long n = SIZE / 4; for (i = 0; i < n; i++) - a[i] = vec_add (b[i], c[i]); + a[i] = b[i] + c[i]; } -#pragma GCC target("vsx") +/* cpu=power7 must be used to enable VSX. */ +#pragma GCC target("cpu=power7,vsx") #ifndef __ALTIVEC__ #error "__ALTIVEC__ should be defined." @@ -53,6 +51,7 @@ av_add (vector float *a, vector float *b, vector float *c) #error "__VSX__ should be defined." #endif +/* VSX build on power7, generate xsaddsp. */ void vsx_add (vector float *a, vector float *b, vector float *c) { @@ -60,11 +59,31 @@ vsx_add (vector float *a, vector float *b, vector float *c) unsigned long n = SIZE / 4; for (i = 0; i < n; i++) - a[i] = vec_add (b[i], c[i]); + a[i] = b[i] + c[i]; +} + +#pragma GCC target("cpu=power7,no-vsx") + +#ifndef __ALTIVEC__ +#error "__ALTIVEC__ should be defined." +#endif + +#ifdef __VSX__ +#error "__VSX__ should not be defined." +#endif + +/* Altivec build on power7 with no VSX, generate vaddfp. */ +void +av2_add (vector float *a, vector float *b, vector float *c) +{ + unsigned long i; + unsigned long n = SIZE / 4; + + for (i = 0; i < n; i++) + a[i] = b[i] + c[i]; } #pragma GCC pop_options -#pragma GCC target("no-vsx,no-altivec") #ifdef __ALTIVEC__ #error "__ALTIVEC__ should not be defined." @@ -74,6 +93,7 @@ vsx_add (vector float *a, vector float *b, vector float *c) #error "__VSX__ should not be defined." #endif +/* Default power5 build, generate scalar fadds. */ void norm_add (float *a, float *b, float *c) { diff --git a/gcc/testsuite/gcc.target/powerpc/pr115688.c b/gcc/testsuite/gcc.target/powerpc/pr115688.c index 5222e66ef17..00c7c301436 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr115688.c +++ b/gcc/testsuite/gcc.target/powerpc/pr115688.c @@ -7,7 +7,8 @@ /* Verify there is no ICE under 32 bit env. */ -__attribute__((target("vsx"))) +/* cpu=power7 must be used to enable VSX. */ +__attribute__((target("cpu=power7,vsx"))) int test (void) { return 0;