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Fri, 2 Aug 2024 06:13:09 GMT Received: from smtpav03.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7D9DB5805A; Fri, 2 Aug 2024 06:13:07 +0000 (GMT) Received: from smtpav03.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 06ECB5803F; Fri, 2 Aug 2024 06:13:07 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.67.12]) by smtpav03.dal12v.mail.ibm.com (Postfix) with ESMTPS; Fri, 2 Aug 2024 06:13:06 +0000 (GMT) Date: Fri, 2 Aug 2024 02:13:03 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner Subject: [PATCH 3/9] Do not allow -mvsx to boost processor to power7. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: gsk7xXEcFaGz4P1G4IftVS2BOFvTv6_p X-Proofpoint-ORIG-GUID: 6DHkxDNAfrWE5BThqvFtve2mZG64-deG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-02_02,2024-08-01_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=999 spamscore=0 adultscore=0 suspectscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408020039 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch restructures the code so that -mvsx for example will not silently convert the processor to power7. The user must now use -mcpu=power7 or higher. This means if the user does -mvsx and the default processor does not have VSX support, it will be an error. I have built both big endian and little endian bootstrap compilers and there were no regressions. In addition, I constructed a test case that used every archiecture define (like _ARCH_PWR4, etc.) and I also looked at the .machine directive generated. I ran this test for all supported combinations of -mcpu, big/little endian, and 32/64 bit support. Every single instance generated exactly the same code with the patches installed compared to the compiler before installing the patches. Can I install this patch on the GCC 15 trunk? 2024-08-01 Michael Meissner gcc/ * config/rs6000/rs6000.cc (report_architecture_mismatch): New function. Report an error if the user used an option such as -mvsx when the default processor would not allow the option. (rs6000_option_override_internal): Move some ISA checking code into report_architecture_mismatch. --- gcc/config/rs6000/rs6000.cc | 129 ++++++++++++++++++++++-------------- 1 file changed, 79 insertions(+), 50 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index caab770cd95..c89a6ea8e79 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1172,6 +1172,7 @@ const int INSN_NOT_AVAILABLE = -1; static void rs6000_print_isa_options (FILE *, int, const char *, HOST_WIDE_INT, HOST_WIDE_INT); static HOST_WIDE_INT rs6000_disable_incompatible_switches (void); +static void report_architecture_mismatch (void); static enum rs6000_reg_type register_to_reg_type (rtx, bool *); static bool rs6000_secondary_reload_move (enum rs6000_reg_type, @@ -3698,7 +3699,6 @@ rs6000_option_override_internal (bool global_init_p) bool ret = true; HOST_WIDE_INT set_masks; - HOST_WIDE_INT ignore_masks; int cpu_index = -1; int tune_index; struct cl_target_option *main_target_opt @@ -3967,59 +3967,13 @@ rs6000_option_override_internal (bool global_init_p) dwarf_offset_size = POINTER_SIZE_UNITS; #endif - /* Handle explicit -mno-{altivec,vsx} and turn off all of - the options that depend on those flags. */ - ignore_masks = rs6000_disable_incompatible_switches (); - - /* For the newer switches (vsx, dfp, etc.) set some of the older options, - unless the user explicitly used the -mno-