diff mbox series

[v2] Improve vsetvl vconfig alignment

Message ID PR3PR08MB57388E6A3430AD56EC0CFBF9BE702@PR3PR08MB5738.eurprd08.prod.outlook.com
State New
Headers show
Series [v2] Improve vsetvl vconfig alignment | expand

Commit Message

Dusan Stojkovic Oct. 2, 2024, 11:57 a.m. UTC 
This patch is a new version of:
https://gcc.gnu.org/pipermail/gcc-patches/2024-September/662745.html

> Can you elaborate a bit on that?  Rearranging the CFG shouldn't matter
> in general and relying on the specific TARGET_SFB_ALU feels overly
> specific.
> Why does the same register in the if_then_else and interfere with vsetvl?

When ce1 pass transforms CFG in the case of the conditional move,
it deletes then and else basic blocks and in their place adds the conditional
move which uses the same pseudo-register as the original vsetvl.

This interferes with vsetvl pass precisely because of the merge policy.
Use by non rvv flag limits the cases where merging might still be possible.
This patch tries to addresses one such issue.

Agreed. I have removed TARGET_SFB_ALU flag from the condition.

> BTW Bohan Lei has since fixed a bug regarding non-RVV uses.  Does the
> situation change with that applied?

Repeated the testing for sifive-7-series as well as rocket. The same tests
are still effected positively: vsetvlmax-9, vsetvlmax-10, vsetvlmax-11, vsetvlmax-15
on sifive-7-series.

2024-10-2  Dusan Stojkovic  <Dusan.Stojkovic@rt-rk.com>

        PR target/113035

gcc/ChangeLog:

        * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): New fuse condition.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Updated scan-assembler-times num parameter.


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---
 gcc/config/riscv/riscv-vsetvl.cc              | 24 +++++++++++++++++++
 .../riscv/rvv/vsetvl/vsetvlmax-15.c           |  2 +-
 2 files changed, 25 insertions(+), 1 deletion(-)

Comments

Dusan Stojkovic Oct. 2, 2024, 12:36 p.m. UTC | #1 
I accidentally forgot to include RISC-V in the title of the patch.
Please ignore this patch since I have sent a fixed one.
https://gcc.gnu.org/pipermail/gcc-patches/2024-October/664305.html
Sorry for the inconvenience.
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 030ffbe2ebb..e2a5231333f 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3061,6 +3061,30 @@  pre_vsetvl::earliest_fuse_vsetvl_info (int iter)
 	  else
 	    {
 	      vsetvl_info &prev_info = src_block_info.get_exit_info ();
+		  if (prev_info.valid_p ()
+		  && curr_info.valid_p ()
+		  && prev_info.vl_used_by_non_rvv_insn_p ()
+		  && !curr_info.vl_used_by_non_rvv_insn_p ())
+		  {
+		    // Try to merge each demand individually
+		    if (m_dem.sew_lmul_compatible_p (prev_info, curr_info))
+		    {
+		      m_dem.merge_sew_lmul (prev_info, curr_info);
+		    }
+		    if (m_dem.policy_compatible_p (prev_info, curr_info))
+		    {
+		      m_dem.merge_policy (prev_info, curr_info);
+		    }
+		    if (dump_file && (dump_flags & TDF_DETAILS))
+		    {
+			  fprintf (dump_file, "    After fusing curr info and "
+					  "prev info demands individually:\n");
+		      fprintf (dump_file, "      prev_info: ");
+		      prev_info.dump (dump_file, "		");
+		      fprintf (dump_file, "      curr_info: ");
+		      curr_info.dump (dump_file, "		");
+		    }
+		  }
 	      if (!prev_info.valid_p ()
 		  || m_dem.available_p (prev_info, curr_info)
 		  || !m_dem.compatible_p (prev_info, curr_info))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
index 23042460885..65aceed0e4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
@@ -18,6 +18,6 @@  void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int c
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
 /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*5} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */