@@ -827,7 +827,10 @@ riscv_expand_block_clear_zicboz_zic64b (rtx dest, rtx length)
{
rtx mem = adjust_address (dest, BLKmode, offset);
rtx addr = force_reg (Pmode, XEXP (mem, 0));
- emit_insn (gen_riscv_zero_di (addr));
+ if (TARGET_64BIT)
+ emit_insn (gen_riscv_zero_di (addr));
+ else
+ emit_insn (gen_riscv_zero_si (addr));
offset += cbo_bytes;
}
@@ -1,6 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */
-/* { dg-options "-march=rv32gc_zic64b_zicboz" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_zic64b_zicboz -mabi=lp64d" } */
/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-allow-blank-lines-in-output 1 } */