| Message ID | 287a4c263f114efd26a0ef9620d0a7ff9833be3f.1733758825.git.dimitar@dinux.eu |
|---|---|
| State | New |
| Headers | show |
| Series | testsuite: RISC-V: Improve support for RV32E | expand |
> +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ > +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ Wouldn't skipping those tests also be reasonable? I.e. adding a target to the compile directive instead. I'd find that a bit more intuitive than overriding the ABI. The same might apply to the other cases you touched. In the end it's probably a question of taste but why if your test target mandates an ABI that cannot compile vector tests, why compile them at all?
On Mon, 09 Dec 2024 09:05:10 PST (-0800), Robin Dapp wrote: >> +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ >> +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ > > Wouldn't skipping those tests also be reasonable? > I.e. adding a target to the compile directive instead. I'd find that a bit > more intuitive than overriding the ABI. > The same might apply to the other cases you touched. In the end it's probably > a question of taste but why if your test target mandates an ABI that cannot > compile vector tests, why compile them at all? Unless I'm missing something, these just add V (and sometimes Zvbb). Those should both be buildable with any ABI that's supported by the base ISA. So I think something else has gone off the rails here. > > -- > Regards > Robin
On Mon, Dec 09, 2024 at 09:40:41AM -0800, Palmer Dabbelt wrote: > On Mon, 09 Dec 2024 09:05:10 PST (-0800), Robin Dapp wrote: > > > +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ > > > +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ > > > > Wouldn't skipping those tests also be reasonable? > > I.e. adding a target to the compile directive instead. I'd find that a bit > > more intuitive than overriding the ABI. > > The same might apply to the other cases you touched. In the end it's probably > > a question of taste but why if your test target mandates an ABI that cannot > > compile vector tests, why compile them at all? > > Unless I'm missing something, these just add V (and sometimes Zvbb). Those > should both be buildable with any ABI that's supported by the base ISA. So > I think something else has gone off the rails here. The way I read the specifications, ILP32E ABI is not compatible with the V extension. See quotes and referenced documents below: - The V vector extension depends upon the Zvl128b and Zve64d extensions [1]. - The Zve64d extension depends upon the D extension [2]. - The ILP32E calling convention is not compatible with ISAs that have registers that require load and store alignments of more than 32 bits. In particular, this calling convention must not be used with the D ISA extension [3] [1] The RISC-V Instruction Set Manual Volume I, Version 20240411 Chapter "31.18.3. V: Vector Extension for Application Processors" [2] The RISC-V Instruction Set Manual Volume I, Version 20240411 Chapter "31.18.2. Zve*: Vector Extensions for Embedded Processors" [3] RISC-V ABIs Specification, Version 1.0: Ratified Chapter "2.3. ILP32E Calling Convention" Regards, Dimitar > > > > > -- > > Regards > > Robin
On Mon, Dec 09, 2024 at 06:05:10PM +0100, Robin Dapp wrote: > > +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ > > +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ > > Wouldn't skipping those tests also be reasonable? > I.e. adding a target to the compile directive instead. I'd find that a bit > more intuitive than overriding the ABI. > The same might apply to the other cases you touched. In the end it's probably > a question of taste but why if your test target mandates an ABI that cannot > compile vector tests, why compile them at all? Yes, it's perfectly reasonable to skip such tests for ILP32E default ABI. I can prepare a patch to filter with "check_effective_target_riscv_e". But instead of adding a new effective_target filter to hundreds of test cases, we could simply prune the test results. Would the bellow approach be acceptable? diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp index 312db38203d..ee1868e2f12 100644 --- a/gcc/testsuite/lib/gcc-dg.exp +++ b/gcc/testsuite/lib/gcc-dg.exp @@ -423,6 +423,10 @@ proc gcc-dg-prune { system text } { return "::unsupported::memory full" } + if { [regexp "(^|\n)\[^\n\]*error: ILP32E ABI does not support the \[^\n\]* extension" $text] + && [check_effective_target_riscv_e] } { + return "::unsupported::ilp32e extension" + } if { [string match "*error: function pointers not supported*" $text] && ![check_effective_target_function_pointers] } { # The format here is important. See dg.exp. diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index f2edbef92da..4f7107b5490 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1904,6 +1904,18 @@ proc check_effective_target_riscv_a { } { }] } +# Return 1 if the target arch has the E extension, 0 otherwise. +# Such support implies that default ABI is either ILP32E or ILP64E. +# Cache the result. + +proc check_effective_target_riscv_e { } { + return [check_no_compiler_messages riscv_ext_e assembly { + #ifndef __riscv_e + #error "Not __riscv_e" + #endif + }] +} + # Return 1 if the target arch supports the atomic LRSC extension, 0 otherwise. # Cache the result. diff --git a/gcc/testsuite/lib/target-utils.exp b/gcc/testsuite/lib/target-utils.exp index 6140ad7cf9f..9a14e4db8e5 100644 --- a/gcc/testsuite/lib/target-utils.exp +++ b/gcc/testsuite/lib/target-utils.exp @@ -48,5 +48,9 @@ proc ${tool}_check_unsupported_p { output } { && ![check_effective_target_large_return_values] } { return "large return values not supported" } + if { [string match "(^|\n)\[^\n\]*error: ILP32E ABI does not support the \[^\n\]* extension" $output] + && [check_effective_target_riscv_e] } { + return "ILP32E ABI does not support an extension" + } return "" }
On 12/10/24 12:48 PM, Dimitar Dimitrov wrote: > On Mon, Dec 09, 2024 at 06:05:10PM +0100, Robin Dapp wrote: >>> +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ >>> +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ >> >> Wouldn't skipping those tests also be reasonable? >> I.e. adding a target to the compile directive instead. I'd find that a bit >> more intuitive than overriding the ABI. >> The same might apply to the other cases you touched. In the end it's probably >> a question of taste but why if your test target mandates an ABI that cannot >> compile vector tests, why compile them at all? > > Yes, it's perfectly reasonable to skip such tests for ILP32E default > ABI. I can prepare a patch to filter with "check_effective_target_riscv_e". > > But instead of adding a new effective_target filter to hundreds of test > cases, we could simply prune the test results. Would the bellow > approach be acceptable? > > diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp > index 312db38203d..ee1868e2f12 100644 > --- a/gcc/testsuite/lib/gcc-dg.exp > +++ b/gcc/testsuite/lib/gcc-dg.exp > @@ -423,6 +423,10 @@ proc gcc-dg-prune { system text } { > return "::unsupported::memory full" > } > > + if { [regexp "(^|\n)\[^\n\]*error: ILP32E ABI does not support the \[^\n\]* extension" $text] > + && [check_effective_target_riscv_e] } { > + return "::unsupported::ilp32e extension" > + } I'd probably recommend against this. You're going to be running that regexp hundreds of thousands of times per test run. I'd rather skip the test or adjust the ABI over pruning.
On 12/10/24 12:48 PM, Dimitar Dimitrov wrote: > On Mon, Dec 09, 2024 at 06:05:10PM +0100, Robin Dapp wrote: >>> +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ >>> +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ >> >> Wouldn't skipping those tests also be reasonable? >> I.e. adding a target to the compile directive instead. I'd find that a bit >> more intuitive than overriding the ABI. >> The same might apply to the other cases you touched. In the end it's probably >> a question of taste but why if your test target mandates an ABI that cannot >> compile vector tests, why compile them at all? > > Yes, it's perfectly reasonable to skip such tests for ILP32E default > ABI. I can prepare a patch to filter with "check_effective_target_riscv_e". I'd say let's go with the original or this proposal. I lean slightly towards this proposal as I can easily see us having tests that are specific to to 32E and having the target selector in place will make that easier. > > But instead of adding a new effective_target filter to hundreds of test > cases, we could simply prune the test results. Would the bellow > approach be acceptable? Let's avoid the pruning approach. jeff
On Sat, Dec 14, 2024 at 10:17:44AM -0700, Jeff Law wrote: > > > On 12/10/24 12:48 PM, Dimitar Dimitrov wrote: > > On Mon, Dec 09, 2024 at 06:05:10PM +0100, Robin Dapp wrote: > > > > +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ > > > > +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ > > > > > > Wouldn't skipping those tests also be reasonable? > > > I.e. adding a target to the compile directive instead. I'd find that a bit > > > more intuitive than overriding the ABI. > > > The same might apply to the other cases you touched. In the end it's probably > > > a question of taste but why if your test target mandates an ABI that cannot > > > compile vector tests, why compile them at all? > > > > Yes, it's perfectly reasonable to skip such tests for ILP32E default > > ABI. I can prepare a patch to filter with "check_effective_target_riscv_e". > I'd say let's go with the original or this proposal. I lean slightly > towards this proposal as I can easily see us having tests that are specific > to to 32E and having the target selector in place will make that easier. > Ack. I'll send a new version with this proposal for effective target filter. Regards, Dimitar > > > > > But instead of adding a new effective_target filter to hundreds of test > > cases, we could simply prune the test results. Would the bellow > > approach be acceptable? > Let's avoid the pruning approach. > > jeff >
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c index 3bb5bf8dd5b..bf7567b23e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c @@ -2,6 +2,8 @@ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ #include "vandn-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c index 55dac27697c..841e2cebefa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c @@ -2,6 +2,8 @@ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ #include "vrolr-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c index a2e5b4f5aa1..1af3c37b3ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c @@ -2,6 +2,8 @@ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ #include "vwsll-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h index 376cbaee0d5..a9f35a54fe0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h @@ -2,6 +2,8 @@ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c index 1fd3644886a..5f98688f916 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c @@ -2,6 +2,8 @@ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-fno-vect-cost-model -fdump-tree-vect-details -mrvv-max-lmul=m4" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c index c27d9d399b9..c03decc5228 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c @@ -2,6 +2,8 @@ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ #include "clz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c index d5989bd5aad..caf4175492a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c @@ -2,6 +2,8 @@ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ #include "ctz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c index 1396e46ec8c..28e369d8acc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-add-options "riscv_v" } */ /* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c index 116cc304da3..d2cbeaf594b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-add-options "riscv_v" } */ /* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ int x[8]; int y[8]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c index 00b87a07fd8..7e261e49d80 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c @@ -2,6 +2,8 @@ /* { dg-add-options "riscv_v" } */ /* { dg-add-options "riscv_zvbb" } */ /* { dg-additional-options "-std=c99 -fno-vect-cost-model" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ #include "popcount-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c index 6bc8b07bc2c..2a3dc84c912 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c index 5ca31af90fb..1d17a5083d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c index 5860b27a233..d3f8210c0b1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c index 81d14d83633..867211056f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-add-options riscv_v } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ /* { dg-final { check-function-bodies "**" "" } } */ #if 0 /* Using include files when using a multilib-relevant -march option is dicey */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c index 7b6a429f34c..98cc21493f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */ /* { dg-add-options riscv_v } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ /* { dg-final { check-function-bodies "**" "" } } */ typedef struct { char c[16]; } c16; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c index f07078ba6a7..4be97c3f2bf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */ /* { dg-add-options riscv_v } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c index 1f148bc7052..926aa0b1ebe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c index 8359e81629d..4d63ef5c916 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-std=gnu99" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ #include <stdint.h> #include <riscv_vector.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c index 22844ff348c..f5b6a3417d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=dynamic" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c index 838fbebadff..8304d723c78 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=m1" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c index 44933819715..ec1114e12af 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-O3 -mrvv-max-lmul=m8" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MIN_VECTOR_BYTES (__riscv_v_min_vlen / 8) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c index 196215a1f7b..9a85f069d85 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-add-options riscv_v } */ /* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-mabi=lp64d" { target { rv64 } } } */ +/* { dg-additional-options "-mabi=ilp32d" { target { rv32 } } } */ #include <stdint.h> #include <riscv_vector.h>
Some tests add options for V and Zvbb extensions, but do not have checks whether the default abi supports them. Fix by explicitly specifying ilp32d and lp64d ABI. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vandn-1.c: Specify ilp32d ABI for RV32 targets, and lp64d for RV64 targets. * gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vwsll-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vwsll-template.h: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/clz-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/ctz-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/popcount-3.c: Ditto. * gcc.target/riscv/rvv/base/cmpmem-1.c: Ditto. * gcc.target/riscv/rvv/base/cmpmem-3.c: Ditto. * gcc.target/riscv/rvv/base/cmpmem-4.c: Ditto. * gcc.target/riscv/rvv/base/cpymem-1.c: Ditto. * gcc.target/riscv/rvv/base/cpymem-2.c: Ditto. * gcc.target/riscv/rvv/base/cpymem-3.c: Ditto. * gcc.target/riscv/rvv/base/movmem-1.c: Ditto. * gcc.target/riscv/rvv/base/pr115068.c: Ditto. * gcc.target/riscv/rvv/base/setmem-1.c: Ditto. * gcc.target/riscv/rvv/base/setmem-2.c: Ditto. * gcc.target/riscv/rvv/base/setmem-3.c: Ditto. * gcc.target/riscv/rvv/base/vwaddsub-1.c: Ditto. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c | 2 ++ .../gcc.target/riscv/rvv/autovec/binop/vwsll-template.h | 2 ++ .../riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c | 2 ++ 22 files changed, 44 insertions(+)