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[2/3] testsuite: RISC-V: Explicitly specify ABI when passing -mcpu=

Message ID 27518172c7d26fd371308149fdcafc3bfe22dd34.1733758825.git.dimitar@dinux.eu
State New
Headers show
Series testsuite: RISC-V: Improve support for RV32E | expand

Commit Message

Dimitar Dimitrov Dec. 9, 2024, 4:13 p.m. UTC
The tests are specifying -mcpu=, but do not explicitly define an ABI.
Thus the test spuriously fail when the toolchain has been built for
RV32E.  Fix by adding the necessary markings.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/pr109508.c: Pass -mabi=lp64d option.
	* gcc.target/riscv/pr114139.c: Ditto.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
---
 gcc/testsuite/gcc.target/riscv/pr109508.c | 2 +-
 gcc/testsuite/gcc.target/riscv/pr114139.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/pr109508.c b/gcc/testsuite/gcc.target/riscv/pr109508.c
index 65f291e17ed..aa69ee675eb 100644
--- a/gcc/testsuite/gcc.target/riscv/pr109508.c
+++ b/gcc/testsuite/gcc.target/riscv/pr109508.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-mcpu=sifive-s76" } */
+/* { dg-options "-mcpu=sifive-s76 -mabi=lp64d" } */
 
 typedef char __attribute__((__vector_size__ (1))) V;
 
diff --git a/gcc/testsuite/gcc.target/riscv/pr114139.c b/gcc/testsuite/gcc.target/riscv/pr114139.c
index 1d4eeb65f5c..bd710d3b6d7 100644
--- a/gcc/testsuite/gcc.target/riscv/pr114139.c
+++ b/gcc/testsuite/gcc.target/riscv/pr114139.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-O2 -fpic -mexplicit-relocs -mcpu=sifive-p450" } */
+/* { dg-options "-O2 -fpic -mexplicit-relocs -mcpu=sifive-p450 -mabi=lp64d" } */
 
 static void *p;
 extern void *a[];