diff mbox series

[3/5] RISC-V Rename internal operand modifier N to n

Message ID 20241209085656.2708230-4-kito.cheng@sifive.com
State New
Headers show
Series New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs | expand

Commit Message

Kito Cheng Dec. 9, 2024, 8:56 a.m. UTC 
Here is a purposal that using N for printing register encoding number,
so let rename the existing internal operand modifier `N` to `n`.

gcc/ChangeLog:

	* config/riscv/corev.md (*cv_branch<mode>): Update modifier.
	(*branch<mode>): Ditto.
	* config/riscv/riscv.cc (riscv_print_operand): Update modifier.
	* config/riscv/riscv.md (*branch<mode>): Update modifier.
---
 gcc/config/riscv/corev.md | 4 ++--
 gcc/config/riscv/riscv.cc | 4 ++--
 gcc/config/riscv/riscv.md | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 02c27043301..3c0e9cecdfb 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -2627,7 +2627,7 @@  (define_insn "*cv_branch<mode>"
   "TARGET_XCVBI"
 {
   if (get_attr_length (insn) == 12)
-    return "cv.b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+    return "cv.b%n1\t%2,%z3,1f; jump\t%l0,ra; 1:";
 
   return "cv.b%C1imm\t%2,%3,%0";
 }
@@ -2645,7 +2645,7 @@  (define_insn "*branch<mode>"
   "TARGET_XCVBI"
 {
   if (get_attr_length (insn) == 12)
-    return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+    return "b%n1\t%2,%z3,1f; jump\t%l0,ra; 1:";
 
   return "b%C1\t%2,%z3,%l0";
 }
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 7860e5fbc23..66caba29564 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6823,7 +6823,7 @@  riscv_asm_output_opcode (FILE *asm_out_file, const char *p)
 	  any outermost HIGH.
    'R'	Print the low-part relocation associated with OP.
    'C'	Print the integer branch condition for comparison OP.
-   'N'	Print the inverse of the integer branch condition for comparison OP.
+   'n'	Print the inverse of the integer branch condition for comparison OP.
    'A'	Print the atomic operation suffix for memory model OP.
    'I'	Print the LR suffix for memory model OP.
    'J'	Print the SC suffix for memory model OP.
@@ -6981,7 +6981,7 @@  riscv_print_operand (FILE *file, rtx op, int letter)
       fputs (GET_RTX_NAME (code), file);
       break;
 
-    case 'N':
+    case 'n':
       /* The RTL names match the instruction names. */
       fputs (GET_RTX_NAME (reverse_condition (code)), file);
       break;
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 3a4cd1d93a0..1eec51c117a 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3215,7 +3215,7 @@  (define_insn "*branch<mode>"
   "!TARGET_XCVBI"
 {
   if (get_attr_length (insn) == 12)
-    return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+    return "b%n1\t%2,%z3,1f; jump\t%l0,ra; 1:";
 
   return "b%C1\t%2,%z3,%l0";
 }