diff mbox series

[v1,6/6] RISC-V: Refine signed vector SAT_TRUNC testcase dump check to tree optimized

Message ID 20241208115620.4179824-6-pan2.li@intel.com
State New
Headers show
Series [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized | expand

Commit Message

Li, Pan2 Dec. 8, 2024, 11:56 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

The sat alu related testcase check the rtl dump for the standard name
like .SAT_TRUNC exist or not.  But the rtl pass expand is somehow
impressionable by the middle-end change or debug information.  Like
below new appearance recently.

Replacing Expressions
_5 replace with --> _5 = .SAT_TRUNC (x_3(D), y_4(D)); [tail call]

After that we need to adjust the dump check time and again.  This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c: Take
	tree-optimized pass for standard name check, and adjust the times.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c    | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c    | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c    | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c     | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c    | 6 +++---
 .../riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c     | 6 +++---
 48 files changed, 141 insertions(+), 141 deletions(-)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
index 51a3b1d065e..53f84b49dff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
index 95a11e96a66..aea91799712 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
index 1f40a2e8fc7..2b464e14e26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
index 4a5bdfc1fd4..7c52fe00bd7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
index 034bff3b34f..7ab441b3050 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
index f437c54508c..5dd207852ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_1(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
index 1a0e2d58dba..a6b755fc059 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
index 88bc1f77cc5..0eaf12a46d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
index d56dd050ab2..62476968a65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
index db23955415f..87ac9a4dbec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
index f9c30fadb48..d198aa18569 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
index a1b21ab805e..9e1d9919d3b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_2(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
index 93304371760..9713893ccf8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
index c17b25fd68b..cfaf32b3c60 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
index 1adc420078c..aa7c278fe80 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
index b215b4dbd63..60cfc282d51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
index 13e68df011a..be605479102 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
index 7bd230393e5..22fe85ecb87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_3(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
index 9b85ac5250f..f1392d27256 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
index 912e2b73526..f132ec67ae8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
index f831f79b05f..2bdce5793c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
index f67afcd4e09..cfe150faddb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
index d0bf273df33..a8db981e904 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
index d7ea8582184..f9a2e103183 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_4(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
index c62175ecbf7..cedb8d4662d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
index 0e5fe79d963..0b72b19eb19 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
index 90f1a3a2f6c..cee4f162f88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
index 69f397a90a7..6522129df2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
index 53a8f86f0f3..bd4d74841ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
index af49f56d192..a1e8ec94bee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_5(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
index f2790d8ead0..62a5b6a65a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
index c68eaf7b45f..972a69ea404 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
index 7f81ee119cf..89f18e05f0a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
index f7da8527824..40bec6bfc9b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
index b3d3d07cc14..1b378d9a982 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
index c16337cdc68..22452992f90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_6(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
index 171efe722a3..be8a470b577 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
index 9d0e1fdd82d..9526ca1c89c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
index 8175a70239c..de1c6bd5e88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
index 2f6a1ea60ee..33576664602 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
index 3862e85b513..5469621276d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
index dcde698db48..86698a86a3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_7(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
index 4fc64a281c4..f38ebdfee29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int16_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
index c80621a1047..5838b7cd44b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int32_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
index a60ff87c8a7..f266f5452ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int32_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
index 1257dc6427e..2f42b1eb224 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int16_t, int64_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
index 9a1fe30bc51..741f6bcab5d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int32_t, int64_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
index 7d6a8e26703..5c7b53c9ad6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c
@@ -1,14 +1,14 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_S_TRUNC_FMT_8(int8_t, int64_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" { target { any-opts
      "-O3"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" { target { any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 2 "optimized" { target { any-opts
      "-O2"
    } } } } */
 /* { dg-final { scan-assembler-times {vnclip\.wi} 3 } } */