[v1,5/6] RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimized

Message ID	20241208115620.4179824-5-pan2.li@intel.com
State	New
Headers	show Return-Path: <gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 98FD9385841D From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li <pan2.li@intel.com> Subject: [PATCH v1 5/6] RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimized Date: Sun, 8 Dec 2024 19:56:19 +0800 Message-ID: <20241208115620.4179824-5-pan2.li@intel.com> In-Reply-To: <20241208115620.4179824-1-pan2.li@intel.com> References: <20241208115620.4179824-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	[v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized \| expand [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized [v1,2/6] RISC-V: Refine unsigned vector SAT_SUB testcase dump check to tree optimized [v1,3/6] RISC-V: Refine unsigned vector SAT_TRUNC testcase dump check to tree optimized [v1,4/6] RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized [v1,5/6] RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimized [v1,6/6] RISC-V: Refine signed vector SAT_TRUNC testcase dump check to tree optimized

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c index 38d10575237..5ae4515d254 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c index b1d0ad03dae..1f845791231 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c index a7cb22d2fb4..f16326651c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c index 28c24296dab..fa9fbe693b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c index 19c76774a9c..c0a220d9b40 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c index 572a4bd1127..367589580b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c index f41e939cd37..80a8470a6bc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c index af21bf3b857..a6ca17c748b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c index 88304e985fa..9fb3646e0e3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c index f5a312e67f4..fb7ca8f6ae3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c index 32757215282..37ac03ccad7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c index 8b3953f1861..d2c95519c1d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c index 7057c6a275e..8c77b34f94d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c index f9c968d6b27..ee2840fefb8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c index cd96056d43c..edf669e6927 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c index 24dfbe94639..b0e9e94277b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c @@ -1,14 +1,14 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_SUB_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" { target { any-opts "-O3" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" { target { any-opts +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" { target { any-opts "-O2" } } } } */ /* { dg-final { scan-assembler-times {vssub\.vv} 1 } } */

[v1,5/6] RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimized

Commit Message

Patch