[v1,4/6] RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized

Message ID	20241208115620.4179824-4-pan2.li@intel.com
State	New
Headers	show Return-Path: <gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DA6B6385841C From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li <pan2.li@intel.com> Subject: [PATCH v1 4/6] [PATCH] RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized Date: Sun, 8 Dec 2024 19:56:18 +0800 Message-ID: <20241208115620.4179824-4-pan2.li@intel.com> In-Reply-To: <20241208115620.4179824-1-pan2.li@intel.com> References: <20241208115620.4179824-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	[v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized \| expand [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized [v1,2/6] RISC-V: Refine unsigned vector SAT_SUB testcase dump check to tree optimized [v1,3/6] RISC-V: Refine unsigned vector SAT_TRUNC testcase dump check to tree optimized [v1,4/6] RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized [v1,5/6] RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimized [v1,6/6] RISC-V: Refine signed vector SAT_TRUNC testcase dump check to tree optimized

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c index 6ef8ecbc170..6147e7ab56e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c index 46a4b6fdbd0..2312b5b6074 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c index 43c0e630624..820bbaca52a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c index cc2bd5c9a79..5fd4741ee47 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c index 4c496300d8e..f838dfc1e29 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c index 34d25f7a46d..64b4d953b29 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c index 28544471a99..2daf299775a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c index 0bba22667e4..7d2c290f18d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c index ccbe65a330e..de121556891 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c index d1c67c8cbe0..187c8b1f62f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c index 49ca8d6d26e..61ca265125a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c index 3a2c887983c..eaffe5f4fd1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c index aa13604ca27..9808fc5be1e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c index 2f47e5ba549..ab691cbc2c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c index 1a943d2404f..30326886a80 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c index 9ec120df69d..928b4b66867 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ #include "vec_sat_arith.h" DEF_VEC_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target { no-opts "-O2" } } } } */ -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ /* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */

[v1,4/6] RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized

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