diff mbox series

[v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized

Message ID 20241208115620.4179824-1-pan2.li@intel.com
State New
Headers show
Series [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized | expand

Commit Message

Li, Pan2 Dec. 8, 2024, 11:56 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

The sat alu related testcase check the rtl dump for the standard name
like .SAT_ADD exist or not.  But the rtl pass expand is somehow
impressionable by the middle-end change or debug information.  Like
below new appearance recently.

Replacing Expressions
_5 replace with --> _5 = .SAT_ADD (x_3(D), y_4(D)); [tail call]

After that we need to adjust the dump check time and again.  This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: Take
	tree-optimized pass for standard name check, and adjust the times.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c  | 6 +++---
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c   | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c   | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c   | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c   | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c   | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c   | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c   | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c  | 4 ++--
 .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c   | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c          | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c          | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c          | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c         | 4 ++--
 .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c          | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c     | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c     | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c     | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c      | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c     | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c     | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c     | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c      | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c     | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c     | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c     | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c      | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c     | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c     | 4 ++--
 .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c      | 4 ++--
 63 files changed, 127 insertions(+), 127 deletions(-)

Comments

Kito Cheng Dec. 9, 2024, 7:10 a.m. UTC | #1 
This patch series is LGTM :)

On Sun, Dec 8, 2024 at 8:01 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> The sat alu related testcase check the rtl dump for the standard name
> like .SAT_ADD exist or not.  But the rtl pass expand is somehow
> impressionable by the middle-end change or debug information.  Like
> below new appearance recently.
>
> Replacing Expressions
> _5 replace with --> _5 = .SAT_ADD (x_3(D), y_4(D)); [tail call]
>
> After that we need to adjust the dump check time and again.  This
> patch would like to switch to tree optimized pass for the standard
> name check, which is more stable up to a point.
>
> The below test suites are passed for this patch.
> * The rv64gcv fully regression test.
>
> It is test only patch and obvious up to a point, will commit it
> directly if no comments in next 48H.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: Take
>         tree-optimized pass for standard name check, and adjust the times.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: Ditto.
>         * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: Ditto.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c  | 6 +++---
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c   | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c   | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c   | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c   | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c   | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c   | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c   | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c  | 4 ++--
>  .../gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c   | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c          | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c          | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c          | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c         | 4 ++--
>  .../riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c          | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c     | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c     | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c     | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c      | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c     | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c     | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c     | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c      | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c     | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c     | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c     | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c      | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c     | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c     | 4 ++--
>  .../rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c      | 4 ++--
>  63 files changed, 127 insertions(+), 127 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
> index 88450517657..440156b7718 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
> @@ -1,11 +1,11 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_1(uint16_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts
>       "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1"
>       "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2"
>       "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m3"
> @@ -15,7 +15,7 @@ DEF_VEC_SAT_U_ADD_FMT_1(uint16_t)
>       "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m3"
>       "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4"
>     } } } } */
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target any-opts
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target any-opts
>       "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1"
>       "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2"
>       "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m3"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
> index c740c693c01..f489480b3d5 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_1(uint32_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
> index 1cc577f6c8b..0a62cbb9a35 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_1(uint64_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
> index ecbc27725c7..70a1d317571 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_1(uint8_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
> index 73a23fadf13..48f3e2ef659 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_2(uint16_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
> index b62f30133e1..8f98b7de58a 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_2(uint32_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
> index 8bb2fbc87a2..ac0bbb02558 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_2(uint64_t)
>
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
> index ffc4342be9b..e90ccdec4c4 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_2(uint8_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
> index effb4d48e27..fe25add43a4 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
> @@ -1,5 +1,5 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
> @@ -13,5 +13,5 @@
>  */
>  DEF_VEC_SAT_U_ADD_FMT_3(uint16_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
> index 1b64fc18a90..3bd74ba2fbc 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_3(uint32_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
> index fdda300d605..b24d1f1d4e2 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_3(uint64_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
> index 35e98475895..fc8b5bb2694 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_3(uint8_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
> index aaac0f0eb28..431cc7b1f37 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_4(uint16_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
> index 6ad6904335c..a35fbf65a43 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_4(uint32_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
> index adb27bbf56c..5b0b80bcdc9 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_4(uint64_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
> index 4b337b3649b..87037af382d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_4(uint8_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
> index acfe5b55884..b27ef0fafed 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_5(uint16_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
> index aba5b0449e8..c28edf490a5 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_5(uint32_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
> index 7d5d8cc99eb..e337b9aceea 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_5(uint64_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
> index 592c976019a..5280c10824c 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_5(uint8_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
> index 1bd4cf5715d..e362d50061c 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_6(uint16_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
> index f358bf4b42a..76fa0359653 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_6(uint32_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
> index 715974ef3a7..671e345ddc7 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_6(uint64_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
> index 055e44d6487..8271797a7f9 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_6(uint8_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
> index e5b5d7e5902..8b7749d7902 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_7(uint16_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
> index be71df2aee7..8a829c7ded6 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_7(uint32_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
> index 442be2109bb..d3973e0421c 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_7(uint64_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
> index a9f9c858c7f..df676f423b5 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_7(uint8_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
> index 7ed1d1211fe..fd88fd23325 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_8(uint16_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
> index 6527af2d210..ee8104b6f8f 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_8(uint32_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
> index 971795cad08..64c742e42a1 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_8(uint64_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
> index 99deffea15b..28eb2d4429c 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_FMT_8(uint8_t)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
> index bd549f7882d..f9421745d68 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint16_t, 15)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
> index 75d5a67e1c8..002c1e35bcb 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint32_t, 33)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
> index 2195dce98ef..a7cb685dee3 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint64_t, 129)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
> index f61df646c73..ade8f4c36f5 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint8_t, 9)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
> index fa99826135c..f3eaf33f341 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint16_t, 15)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
> index a343104a628..8e0da58e98b 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint32_t, 33)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
> index ee8d8e675e3..29db6194503 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint64_t, 129)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
> index b35cdbe9207..fe936f718e0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint8_t, 9)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
> index d8a7da79c5c..09ef00273d5 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 15)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
> index be4e263a956..5c827a8b861 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 33u)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
> index d29807a7981..d8cab1c3e13 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 129ull)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
> index b190b28e344..09441f9e5e4 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 9u)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
> index f528b95fd2c..c9a4ecb0618 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint16_t, 15)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
> index de6570bb32d..0342a734265 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint32_t, 33u)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
> index f2aa70816b3..5e8ce1ff575 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint64_t, 129ull)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
> index a3045ad0a00..5bba140acc4 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint8_t, 9u)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
>  /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
> index 74793603bc2..6bab0fe4da6 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 219)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
> index 38402a34aef..c8f28625b5e 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 299)
>
> -/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
> +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
> index 90b0bff92b7..f822e1ae1b2 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 301u)
>
> -/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
> +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
> index 2aaef2f6636..05cb6379ae0 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 9u)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
> index 94a8e6715bd..e3b7ad25b86 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 65530)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
> index 5c5dc25c72e..78de31badea 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 65559)
>
> -/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
> +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
> index 5d99e79b623..e54b3577b8b 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 75559u)
>
> -/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
> +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
> index 02f07ff0cdc..f5a228dc3ae 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 9u)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
> index 8f18b82819f..aa033b6bf3e 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967205u)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
> index 2ddecd8e005..3127ff16738 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967495ll)
>
> -/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
> +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
> index 222ec989b34..85c7bab13a3 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 9294967495ull)
>
> -/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
> +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
> index 2f6da167c62..04d59118013 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 911u)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
> index 7e2df06ebf4..00ee173df04 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551615ull)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
> index 5ab4f162d84..eb7284e60a9 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 9223372036854775807ull)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
> index 64c112d222d..b910ed87e4e 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
> @@ -1,9 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
>  /* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  #include "vec_sat_arith.h"
>
>  DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 119u)
>
> -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
> +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
> --
> 2.43.0
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
index 88450517657..440156b7718 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
@@ -1,11 +1,11 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_1(uint16_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" { target { no-opts
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts
      "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1"
      "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2"
      "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m3"
@@ -15,7 +15,7 @@  DEF_VEC_SAT_U_ADD_FMT_1(uint16_t)
      "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m3"
      "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4"
    } } } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" { target any-opts
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target any-opts
      "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1"
      "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2"
      "-O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m3"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
index c740c693c01..f489480b3d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_1(uint32_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
index 1cc577f6c8b..0a62cbb9a35 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_1(uint64_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
index ecbc27725c7..70a1d317571 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_1(uint8_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
index 73a23fadf13..48f3e2ef659 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_2(uint16_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
index b62f30133e1..8f98b7de58a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_2(uint32_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
index 8bb2fbc87a2..ac0bbb02558 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_2(uint64_t)
 
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
index ffc4342be9b..e90ccdec4c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_2(uint8_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
index effb4d48e27..fe25add43a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
@@ -13,5 +13,5 @@ 
 */
 DEF_VEC_SAT_U_ADD_FMT_3(uint16_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
index 1b64fc18a90..3bd74ba2fbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_3(uint32_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
index fdda300d605..b24d1f1d4e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_3(uint64_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
index 35e98475895..fc8b5bb2694 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_3(uint8_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
index aaac0f0eb28..431cc7b1f37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_4(uint16_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
index 6ad6904335c..a35fbf65a43 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_4(uint32_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
index adb27bbf56c..5b0b80bcdc9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_4(uint64_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
index 4b337b3649b..87037af382d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_4(uint8_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
index acfe5b55884..b27ef0fafed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_5(uint16_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
index aba5b0449e8..c28edf490a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_5(uint32_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
index 7d5d8cc99eb..e337b9aceea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_5(uint64_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
index 592c976019a..5280c10824c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_5(uint8_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
index 1bd4cf5715d..e362d50061c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_6(uint16_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
index f358bf4b42a..76fa0359653 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_6(uint32_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
index 715974ef3a7..671e345ddc7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_6(uint64_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
index 055e44d6487..8271797a7f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_6(uint8_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
index e5b5d7e5902..8b7749d7902 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_7(uint16_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
index be71df2aee7..8a829c7ded6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_7(uint32_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
index 442be2109bb..d3973e0421c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_7(uint64_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
index a9f9c858c7f..df676f423b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_7(uint8_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
index 7ed1d1211fe..fd88fd23325 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_8(uint16_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
index 6527af2d210..ee8104b6f8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_8(uint32_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
index 971795cad08..64c742e42a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_8(uint64_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
index 99deffea15b..28eb2d4429c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_FMT_8(uint8_t)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
index bd549f7882d..f9421745d68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint16_t, 15)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
index 75d5a67e1c8..002c1e35bcb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint32_t, 33)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
index 2195dce98ef..a7cb685dee3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint64_t, 129)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
index f61df646c73..ade8f4c36f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint8_t, 9)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
index fa99826135c..f3eaf33f341 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint16_t, 15)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
index a343104a628..8e0da58e98b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint32_t, 33)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
index ee8d8e675e3..29db6194503 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint64_t, 129)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
index b35cdbe9207..fe936f718e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint8_t, 9)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
index d8a7da79c5c..09ef00273d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 15)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
index be4e263a956..5c827a8b861 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 33u)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
index d29807a7981..d8cab1c3e13 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 129ull)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
index b190b28e344..09441f9e5e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 9u)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
index f528b95fd2c..c9a4ecb0618 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint16_t, 15)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
index de6570bb32d..0342a734265 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint32_t, 33u)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
index f2aa70816b3..5e8ce1ff575 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint64_t, 129ull)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
index a3045ad0a00..5bba140acc4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint8_t, 9u)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
 /* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
index 74793603bc2..6bab0fe4da6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 219)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
index 38402a34aef..c8f28625b5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 299)
 
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
index 90b0bff92b7..f822e1ae1b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 301u)
 
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
index 2aaef2f6636..05cb6379ae0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 9u)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
index 94a8e6715bd..e3b7ad25b86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 65530)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
index 5c5dc25c72e..78de31badea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 65559)
 
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
index 5d99e79b623..e54b3577b8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 75559u)
 
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
index 02f07ff0cdc..f5a228dc3ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 9u)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
index 8f18b82819f..aa033b6bf3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967205u)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
index 2ddecd8e005..3127ff16738 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 4294967495ll)
 
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
index 222ec989b34..85c7bab13a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 9294967495ull)
 
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
index 2f6da167c62..04d59118013 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 911u)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
index 7e2df06ebf4..00ee173df04 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 18446744073709551615ull)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
index 5ab4f162d84..eb7284e60a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 9223372036854775807ull)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
index 64c112d222d..b910ed87e4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */
 /* { dg-skip-if "" { *-*-* } { "-flto" } } */
 
 #include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 119u)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */