diff mbox series

[v1,4/6] RISC-V: Refine signed SAT_ADD testcase dump check to tree optimized

Message ID 20241208013230.3579529-4-pan2.li@intel.com
State New
Headers show
Series [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized | expand

Commit Message

Li, Pan2 Dec. 8, 2024, 1:32 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

The sat alu related testcase check the rtl dump for the standard name
like .SAT_ADD exist or not.  But the rtl pass expand is somehow
impressionable by the middle-end change or debug information.  Like
below new appearance recently.

Replacing Expressions
_5 replace with --> _5 = .SAT_ADD (x_3(D), y_4(D)); [tail call]

After that we need to adjust the dump check time and again.  This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_s_add-1-i16.c: Take tree-optimized
	pass for standard name check, and adjust the times.
	* gcc.target/riscv/sat/sat_s_add-1-i32.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-1-i64.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-1-i8.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-2-i16.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-2-i32.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-2-i64.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-2-i8.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-3-i16.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-3-i32.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-3-i64.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-3-i8.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-4-i16.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-4-i32.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-4-i64.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add-4-i8.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-1-1.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-1.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-2-1.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-2.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-3-1.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-3.c: Ditto.
	* gcc.target/riscv/sat/sat_s_add_imm-4.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c    | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c    | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c    | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c    | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-1.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-1.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3-1.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c   | 4 ++--
 23 files changed, 46 insertions(+), 46 deletions(-)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c
index 24832c7435d..55890d8487c 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -29,4 +29,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c
index ea0a757cff8..29e843f3c7b 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -28,4 +28,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c
index 85c0087d7d0..7f29d21d103 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -26,4 +26,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c
index 3941829543e..3ad7bdd9164 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -27,4 +27,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c
index acbc50e5396..07d31015c13 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -29,4 +29,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c
index af22c34ca15..81b85b4ab6e 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -28,4 +28,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c
index 2bb929385f2..9a3d83e8edc 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -26,4 +26,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c
index 76f318b4ec1..ecc9a0f733c 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -27,4 +27,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c
index 2abeb033a21..7e933856e71 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -29,4 +29,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c
index e5c74e5f84b..09bf497cc10 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -28,4 +28,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c
index 017efeda1db..5652cdb9aea 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -26,4 +26,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c
index 8ced9e2592d..0eb0c849649 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -27,4 +27,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c
index 5fdbd135d4b..9dfdb9eba9a 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -29,4 +29,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c
index 6fe98578f50..74df576b531 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -28,4 +28,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c
index dd4d3e80121..5937699766f 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -26,4 +26,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c
index eef05807a11..af850d0d155 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -27,4 +27,4 @@ 
 */
 DEF_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-1.c
index a54bb94717d..84c6bc7da14 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-1.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-1.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "sat_arith.h"
 
 DEF_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, -129, INT8_MIN, INT8_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(1, int8_t, uint8_t, 128, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c
index 154992b6a14..b6f1731352c 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -26,4 +26,4 @@ 
 */
 DEF_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-1.c
index 960766f4383..e9f708038c6 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-1.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-1.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "sat_arith.h"
 
 DEF_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -32769, INT16_MIN, INT16_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(1, int16_t, uint16_t, 32768, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c
index ebcfedd790a..3878286d207 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -29,4 +29,4 @@ 
 */
 DEF_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -7, INT16_MIN, INT16_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3-1.c
index 9a6254b7732..9dae4254d31 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3-1.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3-1.c
@@ -1,9 +1,9 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
 
 #include "sat_arith.h"
 
 DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, -2147483649, INT32_MIN, INT32_MAX)
 DEF_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, 2147483648, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c
index 371ba472955..c9fbc665562 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -27,4 +27,4 @@ 
 */
 DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, 10, INT32_MIN, INT32_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c
index 27320b550b2..2aa954585e7 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c
@@ -1,5 +1,5 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "sat_arith.h"
@@ -25,4 +25,4 @@ 
 */
 DEF_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, 10, INT64_MIN, INT64_MAX)
 
-/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */