From patchwork Wed Oct 16 16:23:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eikansh Gupta X-Patchwork-Id: 1998166 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=KL5BRoob; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XTGVk1DL7z1xth for ; Thu, 17 Oct 2024 03:23:42 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 501573858D37 for ; Wed, 16 Oct 2024 16:23:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by sourceware.org (Postfix) with ESMTPS id C18D03858D20 for ; Wed, 16 Oct 2024 16:23:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C18D03858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=quicinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C18D03858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1729095799; cv=none; b=WrLyr6UFd2yTtkQxPDNVgUNPe+ZWiUWaUcNDL6yobXjHKeqPJ9m5/GzIFXu4P6Ge5JzHh/91L/ro7Sl98uAwxevb1A3umzg9EF3fVADfNBx/FnhQ6/AxHIahnBsmLFwH7kd6ktF9B6dMff8di7LjyXQMMLubIVE16krb56WvMBY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1729095799; c=relaxed/simple; bh=iZMPelITNhkAFadcxkD9HZ9cNQY+VzwwpWsIoMxRy8I=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=aupTBo0101/nlhJsdWuCxQ2/Vn78fePzbxDW/I/jArPkHloEam5y5iN/zR4jGg2ozN1SC/UP+1+6mk2wuG6EPuk8zTtYfgC+VVD6GFoGMfkudDl7y25u+PrvnPTkLmaURo4Tj+ZCvOhUTzyDNR8GEY0j/wklK5/PkZFMQtocKb0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49GA0lIk013221 for ; Wed, 16 Oct 2024 16:23:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:message-id:mime-version:subject:to; s= qcppdkim1; bh=cvOzYVWXzUs9uHGgoOmX0tgxffnNLolBylQb0xsfiFU=; b=KL 5BRoobVq/1monArZA5pD1H6CUiOmnaSyDTh8gHLL/pZn5zXg13h3GncIgy2zdbGw 0UhUI5IY7lzKpWaLtrLQRzVglWEPlnxMzaXTWnUloTy8/oh+Omp9HmPIN87O6tvV 0HiW8RtlNASbWV8FtdN1RZmWJnVt3XDToj+BpBPwHRI5dGK6qzSsZLr18J4d9NqR /LtNg5tybsMD9AwNDTxVYSu/kt1DJF4KP5iwOX6X+pXJlauEgq7ptiYM2fGoZmns lAuJTunQ2ie3ttTn589gaHEfEaaxE0r8XvtNSUh/SRde6QjQr90ot38xmsvRFj3l Vq8eFNDhLAgbPzi+enSg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42abbxs7m6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 16 Oct 2024 16:23:17 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49GGNFT8016567 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 16 Oct 2024 16:23:15 GMT Received: from hu-eikagupt-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 16 Oct 2024 09:23:14 -0700 From: Eikansh Gupta To: CC: Eikansh Gupta Subject: [PATCH v3] MATCH: Simplify `a rrotate (32-b) -> a lrotate b` [PR109906] Date: Wed, 16 Oct 2024 21:53:00 +0530 Message-ID: <20241016162300.13929-1-quic_eikagupt@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Ti1xGZt05SggfAOBNrlc-GXChmSWqg0r X-Proofpoint-GUID: Ti1xGZt05SggfAOBNrlc-GXChmSWqg0r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410160104 X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The pattern `a rrotate (32-b)` should be optimized to `a lrotate b`. The same is also true for `a lrotate (32-b)`. It can be optimized to `a rrotate b`. This patch adds following patterns: a rrotate (32-b) -> a lrotate b a lrotate (32-b) -> a rrotate b Bootstrapped and tested on x86_64-linux-gnu with no regressions. PR tree-optimization/109906 gcc/ChangeLog: * match.pd (a rrotate (32-b) -> a lrotate b): New pattern (a lrotate (32-b) -> a rrotate b): New pattern gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/pr109906.c: New test. Signed-off-by: Eikansh Gupta --- gcc/match.pd | 9 ++++++ gcc/testsuite/gcc.dg/tree-ssa/pr109906.c | 41 ++++++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr109906.c diff --git a/gcc/match.pd b/gcc/match.pd index 5ec31ef6269..078ef050351 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -4861,6 +4861,15 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) build_int_cst (TREE_TYPE (@1), element_precision (type)), @1); })) +/* a rrotate (32-b) -> a lrotate b */ +/* a lrotate (32-b) -> a rrotate b */ +(for rotate (lrotate rrotate) + orotate (rrotate lrotate) + (simplify + (rotate @0 (minus INTEGER_CST@1 @2)) + (if (TYPE_PRECISION (TREE_TYPE (@0)) == wi::to_wide (@1)) + (orotate @0 @2)))) + /* Turn (a OP c1) OP c2 into a OP (c1+c2). */ (for op (lrotate rrotate rshift lshift) (simplify diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr109906.c b/gcc/testsuite/gcc.dg/tree-ssa/pr109906.c new file mode 100644 index 00000000000..9aa015d8c65 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr109906.c @@ -0,0 +1,41 @@ +/* PR tree-optimization/109906 */ +/* { dg-do compile } */ +/* { dg-options "-O1 -fdump-tree-optimized-raw" } */ +/* { dg-require-effective-target int32 } */ + +/* Implementation of rotate right operation */ +static inline +unsigned rrotate(unsigned x, int t) +{ + if (t >= 32) __builtin_unreachable(); + unsigned tl = x >> (t); + unsigned th = x << (32 - t); + return tl | th; +} + +/* Here rotate left is achieved by doing rotate right by (32 - x) */ +unsigned rotateleft(unsigned t, int x) +{ + return rrotate (t, 32 - x); +} + +/* Implementation of rotate left operation */ +static inline +unsigned lrotate(unsigned x, int t) +{ + if (t >= 32) __builtin_unreachable(); + unsigned tl = x << (t); + unsigned th = x >> (32 - t); + return tl | th; +} + +/* Here rotate right is achieved by doing rotate left by (32 - x) */ +unsigned rotateright(unsigned t, int x) +{ + return lrotate (t, 32 - x); +} + +/* Shouldn't have instruction for (32 - x). */ +/* { dg-final { scan-tree-dump-not "minus_expr" "optimized" } } */ +/* { dg-final { scan-tree-dump "rrotate_expr" "optimized" } } */ +/* { dg-final { scan-tree-dump "lrotate_expr" "optimized" } } */