| Message ID | 20241002171339.299940-3-andre.simoesdiasvieira@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | aarch64: remove SVE2 requirement from SME and diagnose it as unsupported | expand |
Hi Andre, > On 2 Oct 2024, at 19:13, Andre Vieira <andre.simoesdiasvieira@arm.com> wrote: > > External email: Use caution opening links or attachments > > > As per the AArch64 ISA FEAT_SME does not require FEAT_SVE2, so we are removing > that false dependency in GCC. However, we chose for now to not support this > combination of features and will diagnose the combination of FEAT_SME without > FEAT_SVE2 as unsupported by GCC. We may choose to support this in the future. > > gcc/ChangeLog: > > * config/aarch64/aarch64-arches.def (SME): Remove SVE2 as prerequisite > and add in FCMA and F16FML. > * config/aarch64/aarch64.cc (aarch64_override_options): Diagnose use of > SME without SVE2. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c: > Pass +sve2 to existing +sme pragma. > * gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c: > Likewise. > * gcc.target/aarch64/sve/acle/general-c/binary_single_1.c: Likewise. > * gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c: Likewise. > * gcc.target/aarch64/sve/acle/general-c/clamp_1.c: Likewise. > * gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c: > Likewise. > * gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c: > Likewise. > * gcc.target/aarch64/sve/acle/general-c/storexn_1.c: Likewise. > * gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c: > Likewise. > * gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c: Likewise. > * gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c: Likewise. > --- > gcc/config/aarch64/aarch64-option-extensions.def | 3 ++- > gcc/config/aarch64/aarch64.cc | 4 ++++ > .../aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c | 2 +- > .../aarch64/sve/acle/general-c/binary_opt_single_n_2.c | 2 +- > .../gcc.target/aarch64/sve/acle/general-c/binary_single_1.c | 2 +- > .../gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c | 2 +- > gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c | 2 +- > .../aarch64/sve/acle/general-c/compare_scalar_count_1.c | 2 +- > .../aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c | 2 +- > .../gcc.target/aarch64/sve/acle/general-c/storexn_1.c | 2 +- > .../aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c | 2 +- > .../gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c | 2 +- > .../gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c | 2 +- > 13 files changed, 17 insertions(+), 12 deletions(-) > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 68913beaee2..bc2023da180 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -18998,6 +18998,10 @@ aarch64_override_options (void) while processing functions with potential target attributes. */ target_option_default_node = target_option_current_node = build_target_option_node (&global_options, &global_options_set); + + if (TARGET_SME && !TARGET_SVE2) + warning (0, "this gcc version does not guarantee full support for +sme" + " without +sve2"); } Beyond my comments on the cover letter, if you do intend to give some message here anyway, this can be more fancy :) You can use %qs to quote the +sme and +sve2 strings and I don’t think we usually refer to GCC itself from warnings. I think a passive voice would fit better. Regardless of what we do for the warning this restriction should be documented in doc/invoke.texi if we end up having it for the GCC 15.1 release. Thanks, Kyrill
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 4732c20ec96..e38a4ab3f78 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -192,9 +192,10 @@ AARCH64_OPT_EXTENSION("sve2-sm4", SVE2_SM4, (SVE2, SM4), (), (), "svesm4") AARCH64_FMV_FEATURE("sve2-sm4", SVE_SM4, (SVE2_SM4)) -AARCH64_OPT_FMV_EXTENSION("sme", SME, (BF16, SVE2), (), (), "sme") AARCH64_OPT_EXTENSION("", FCMA, (), (), (), "fcma") +AARCH64_OPT_FMV_EXTENSION("sme", SME, (BF16, FCMA, F16FML), (), (), "sme") + AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "") AARCH64_OPT_FMV_EXTENSION("sb", SB, (), (), (), "sb") diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 68913beaee2..bc2023da180 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -18998,6 +18998,10 @@ aarch64_override_options (void) while processing functions with potential target attributes. */ target_option_default_node = target_option_current_node = build_target_option_node (&global_options, &global_options_set); + + if (TARGET_SME && !TARGET_SVE2) + warning (0, "this gcc version does not guarantee full support for +sme" + " without +sve2"); } /* Implement targetm.override_options_after_change. */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c index 976d5af7f23..7150d37a2aa 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c index 5cc8a4c5c50..2823264edbd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_opt_single_n_2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c index aa7633bb322..52f2c090f57 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binary_single_1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" #include <arm_sve.h> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c index 600b7fc7959..4f8ebf8c2c7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svbool_t pg, svcount_t pn, svuint8_t u8, svint16_t s16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c index 07e22d2dd71..958c40a2fc6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svcount_t pn, svfloat16_t f16, svint16_t s16, svfloat32_t f32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c index 47077f7a4e5..4a4222c1e82 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/compare_scalar_count_1.c @@ -3,7 +3,7 @@ #include <arm_sve.h> #include <stdbool.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" enum signed_enum { SA = -1, SB }; enum unsigned_enum { UA, UB }; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c index ab5602f0aa6..685d0700400 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target ("+sme2") +#pragma GCC target ("+sve2+sme2") void f1 (svboolx2_t pgx2, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c index 7ad4ca8a580..ba0096b4b4b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/storexn_1.c @@ -3,7 +3,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" struct s { signed char x; }; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c index b8968c878e1..5579e0d11b0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c @@ -2,7 +2,7 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void f1 (svbool_t pg, svint8_t s8, svuint8_t u8, svint16_t s16, svuint16_t u16, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c index 85f8b45032d..e14ec71f0c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c @@ -1,6 +1,6 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void test (svbool_t pg, float f, svint8_t s8, svfloat32_t f32, diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c index f478945562c..e9656bc69af 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c @@ -1,6 +1,6 @@ #include <arm_sve.h> -#pragma GCC target "+sme2" +#pragma GCC target "+sve2+sme2" void test (svfloat32_t f32, svfloat32x2_t f32x2, svfloat32x3_t f32x3,