Show patches with: Submitter = Li, Pan2       |    State = Action Required       |    Archived = No       |   600 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v1] RISC-V: Avoid scalar unsigned SAT_ADD test data duplication [v1] RISC-V: Avoid scalar unsigned SAT_ADD test data duplication - - - - --- 2025-05-16 Li, Pan2 New
[v1,10/10] RISC-V: Reuse test name for vx combine test data [NFC] RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-13 Li, Pan2 New
[v1,09/10] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 2 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-13 Li, Pan2 New
[v1,08/10] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-13 Li, Pan2 New
[v1,07/10] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-13 Li, Pan2 New
[v1,06/10] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-13 Li, Pan2 New
[v1,05/10] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-13 Li, Pan2 New
[v1,04/10] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-13 Li, Pan2 New
[v1,03/10] RISC-V: Adjust vx combine test case to avoid name conflict RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-13 Li, Pan2 New
[v1,02/10] RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combine [NFC] RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-13 Li, Pan2 New
[v1,01/10] RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-13 Li, Pan2 New
[v1,7/7] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 2 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-11 Li, Pan2 New
[v1,6/7] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-11 Li, Pan2 New
[v1,5/7] RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-11 Li, Pan2 New
[v1,4/7] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-11 Li, Pan2 New
[v1,3/7] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-11 Li, Pan2 New
[v1,2/7] RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0 RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-11 Li, Pan2 New
[v1,1/7] RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost - - - - --- 2025-05-11 Li, Pan2 New
[v1,5/5] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 2 Add testcases for another case of vec_duplicate + vadd.vv combine - - - - --- 2025-05-08 Li, Pan2 New
[v1,4/5] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 1 Add testcases for another case of vec_duplicate + vadd.vv combine - - - - --- 2025-05-08 Li, Pan2 New
[v1,3/5] RISC-V: Add testcases for vec_duplicate + vadd.vv combine case 1 with GR2VR cost 0 Add testcases for another case of vec_duplicate + vadd.vv combine - - - - --- 2025-05-08 Li, Pan2 New
[v1,2/5] RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0 Add testcases for another case of vec_duplicate + vadd.vv combine - - - - --- 2025-05-08 Li, Pan2 New
[v1,1/5] RISC-V: Separate the test running of rvv vx_vf Add testcases for another case of vec_duplicate + vadd.vv combine - - - - --- 2025-05-08 Li, Pan2 New
[v4,6/6] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 15 RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-05-06 Li, Pan2 New
[v4,5/6] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 1 RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-05-06 Li, Pan2 New
[v4,4/6] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 0 RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-05-06 Li, Pan2 New
[v4,3/6] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-05-06 Li, Pan2 New
[v4,2/6] RISC-V: Add gr2vr cost helper function RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-05-06 Li, Pan2 New
[v4,1/6] RISC-V: Add new option --param=gpr2vr-cost= for rvv insn RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-05-06 Li, Pan2 New
[v1,5/5] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 15 RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-05-03 Li, Pan2 New
[v1,4/5] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 1 RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-05-03 Li, Pan2 New
[v1,3/5] RISC-V: Add testcases for vec_duplicate + vadd.vv combine when GR2VR cost 0 RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-05-03 Li, Pan2 New
[v1,2/5] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-05-03 Li, Pan2 New
[v1,1/5] RISC-V: Add new option --param=rvv-gr2vr-cost= for rvv insn RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-05-03 Li, Pan2 New
[v1,3/3] RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7 Support form 7 of unsigned integer SAT_ADD - - - - --- 2025-04-28 Li, Pan2 New
[v1,2/3] RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7 Support form 7 of unsigned integer SAT_ADD - - - - --- 2025-04-28 Li, Pan2 New
[v1,1/3] Match: Support form 7 for unsigned integer SAT_ADD Support form 7 of unsigned integer SAT_ADD - - - - --- 2025-04-28 Li, Pan2 New
[v1,4/4] RISC-V: Extract vector stepped for expand_const_vector [NFC] Refactor long function expand_const_vector - - - - --- 2025-04-23 Li, Pan2 New
[v1,3/4] RISC-V: Extract vector duplicate for expand_const_vector [NFC] Refactor long function expand_const_vector - - - - --- 2025-04-23 Li, Pan2 New
[v1,2/4] RISC-V: Extract vec_series for expand_const_vector [NFC] Refactor long function expand_const_vector - - - - --- 2025-04-23 Li, Pan2 New
[v1,1/4] RISC-V: Extract vec_duplicate for expand_const_vector [NFC] Refactor long function expand_const_vector - - - - --- 2025-04-23 Li, Pan2 New
[v2,3/3] RISC-V: Add testcases for vec_duplicate + vadd.vv combine to vadd.vx Introduce vec_dup + vadd.vv combine to vadd.vx - - - - --- 2025-04-19 Li, Pan2 New
[v2,2/3] RISC-V: Adjust the testcases after vec_duplicate + vadd.vv combine Introduce vec_dup + vadd.vv combine to vadd.vx - - - - --- 2025-04-19 Li, Pan2 New
[v2,1/3] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost Introduce vec_dup + vadd.vv combine to vadd.vx - - - - --- 2025-04-19 Li, Pan2 New
[3/3,GCC16-Stage-1] RISC-V: Add testcases for vec_duplicate + vadd.vv combine to vadd.vx [1/3,GCC16-Stage-1] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-04-17 Li, Pan2 New
[2/3,GCC16-Stage-1] RISC-V: Adjust the testcases after vec_duplicate + vadd.vv combine [1/3,GCC16-Stage-1] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-04-17 Li, Pan2 New
[1/3,GCC16-Stage-1] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost [1/3,GCC16-Stage-1] RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR cost - - - - --- 2025-04-17 Li, Pan2 New
[v1,GCC16-Stage-1] RISC-V: Remove unnecessary frm restore volatile define_insn [v1,GCC16-Stage-1] RISC-V: Remove unnecessary frm restore volatile define_insn - - - - --- 2025-04-16 Li, Pan2 New
[v1] RISC-V: Refine the testcases for cond_widen_complicate-3 [v1] RISC-V: Refine the testcases for cond_widen_complicate-3 - - - - --- 2025-03-12 Li, Pan2 New
[v1] RISC-V: Tweak asm check for test case multiple_rgroup_zbb.c [v1] RISC-V: Tweak asm check for test case multiple_rgroup_zbb.c - - - - --- 2025-03-06 Li, Pan2 New
[v1] RISC-V: Fix the test case bug-3.c failure [v1] RISC-V: Fix the test case bug-3.c failure - - - - --- 2025-03-03 Li, Pan2 New
[v5] RISC-V: Fix bug for expand_const_vector interleave [PR118931] [v5] RISC-V: Fix bug for expand_const_vector interleave [PR118931] - - - - --- 2025-02-27 Li, Pan2 New
[v4] RISC-V: Fix bug for expand_const_vector interleave [PR118931] [v4] RISC-V: Fix bug for expand_const_vector interleave [PR118931] - - - - --- 2025-02-27 Li, Pan2 New
[v3] RISC-V: Fix bug for expand_const_vector interleave [PR118931] [v3] RISC-V: Fix bug for expand_const_vector interleave [PR118931] - - - - --- 2025-02-26 Li, Pan2 New
[v2] RISC-V: Fix bug for expand_const_vector interleave [PR118931] [v2] RISC-V: Fix bug for expand_const_vector interleave [PR118931] - - - - --- 2025-02-25 Li, Pan2 New
[v1] RISC-V: Fix bug for expand_const_vector interleave [PR118931] [v1] RISC-V: Fix bug for expand_const_vector interleave [PR118931] - - - - --- 2025-02-23 Li, Pan2 New
[v2] Vect: Fix ICE when vect_verify_loop_lens acts on relevant mode [PR116351] [v2] Vect: Fix ICE when vect_verify_loop_lens acts on relevant mode [PR116351] - - - - --- 2025-02-19 Li, Pan2 New
[v1] Vect: Fix ICE when get DImode from get_related_vectype_for_scalar_type [PR116351] [v1] Vect: Fix ICE when get DImode from get_related_vectype_for_scalar_type [PR116351] - - - - --- 2025-02-17 Li, Pan2 New
[v1] RISC-V: Fix ICE for target attributes has different xlen size [v1] RISC-V: Fix ICE for target attributes has different xlen size - - - - --- 2025-02-15 Li, Pan2 New
[v1] RISC-V: Make VXRM as global register [PR118103] [v1] RISC-V: Make VXRM as global register [PR118103] - - - - --- 2025-02-07 Li, Pan2 New
[v3,4/4] RISC-V: Fix incorrect code gen for scalar signed SAT_TRUNC [PR117688] [v3,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - - - --- 2025-01-27 Li, Pan2 New
[v3,3/4] RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688] [v3,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - - - --- 2025-01-27 Li, Pan2 New
[v3,2/4] RISC-V: Fix incorrect code gen for scalar signed SAT_ADD [PR117688] [v3,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - - - --- 2025-01-27 Li, Pan2 New
[v3,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] [v3,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - - - --- 2025-01-27 Li, Pan2 New
[v1] RISC-V: Remove unnecessary frm restore volatile define_insn [v1] RISC-V: Remove unnecessary frm restore volatile define_insn - - - - --- 2025-01-26 Li, Pan2 New
[v2] RISC-V: Make FRM as global register [PR118103] [PR118646] [v2] RISC-V: Make FRM as global register [PR118103] [PR118646] - - - - --- 2025-01-26 Li, Pan2 New
[v1] RISC-V: Make FRM as global register [PR118103] [PR118646] [v1] RISC-V: Make FRM as global register [PR118103] [PR118646] - - - - --- 2025-01-25 Li, Pan2 New
[v2,4/4] RISC-V: Fix incorrect code gen for scalar signed SAT_TRUNC [PR117688] [v2,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - - - --- 2025-01-23 Li, Pan2 New
[v2,3/4] RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688] [v2,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - - - --- 2025-01-23 Li, Pan2 New
[v2,2/4] RISC-V: Fix incorrect code gen for scalar signed SAT_ADD [PR117688] [v2,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - - - --- 2025-01-23 Li, Pan2 New
[v2,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] [v2,1/4] RISC-V: Refactor SAT_* operand rtx extend to reg help func [NFC] - - - - --- 2025-01-23 Li, Pan2 New
[v1] RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688] [v1] RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688] - - - - --- 2025-01-20 Li, Pan2 New
[v1] RISC-V: Fix the the operand alignment for strided load/store pattern [NFC] [v1] RISC-V: Fix the the operand alignment for strided load/store pattern [NFC] - - - - --- 2024-12-20 Li, Pan2 New
[v1] RISC-V: Refine strided load/store testcase dump check to tree optimized [v1] RISC-V: Refine strided load/store testcase dump check to tree optimized - - - - --- 2024-12-20 Li, Pan2 New
[v1,2/2] RISC-V: Adjust the strided store testcases check times on options [v1,1/2] RISC-V: Make vector strided store alias all other memories - - - - --- 2024-12-19 Li, Pan2 New
[v1,1/2] RISC-V: Make vector strided store alias all other memories [v1,1/2] RISC-V: Make vector strided store alias all other memories - - - - --- 2024-12-19 Li, Pan2 New
[v1] RISC-V: Make vector strided load alias all other memories [v1] RISC-V: Make vector strided load alias all other memories - - - - --- 2024-12-13 Li, Pan2 New
[v1,4/4] Match: Update the comments for indicating SAT_* pattern [v1,1/4] Match: Refactor the signed SAT_SUB match patterns [NFC] - - - - --- 2024-12-12 Li, Pan2 New
[v1,3/4] Match: Refactor the signed SAT_* match for saturated value [NFC] [v1,1/4] Match: Refactor the signed SAT_SUB match patterns [NFC] - - - - --- 2024-12-12 Li, Pan2 New
[v1,2/4] Match: Refactor the signed SAT_TRUNC match patterns [NFC] [v1,1/4] Match: Refactor the signed SAT_SUB match patterns [NFC] - - - - --- 2024-12-12 Li, Pan2 New
[v1,1/4] Match: Refactor the signed SAT_SUB match patterns [NFC] [v1,1/4] Match: Refactor the signed SAT_SUB match patterns [NFC] - - - - --- 2024-12-12 Li, Pan2 New
[v1] Match: Refactor the signed SAT_ADD match patterns [NFC] [v1] Match: Refactor the signed SAT_ADD match patterns [NFC] - - - - --- 2024-12-10 Li, Pan2 New
[v1] RISC-V: Fix incorrect optimization options passing to partial [v1] RISC-V: Fix incorrect optimization options passing to partial - - - - --- 2024-12-09 Li, Pan2 New
[v1,6/6] RISC-V: Refine signed vector SAT_TRUNC testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,5/6] RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,4/6] RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,3/6] RISC-V: Refine unsigned vector SAT_TRUNC testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,2/6] RISC-V: Refine unsigned vector SAT_SUB testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,6/6] RISC-V: Refine signed SAT_TRUNC testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,5/6] RISC-V: Refine signed SAT_SUB testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,4/6] RISC-V: Refine signed SAT_ADD testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,3/6] RISC-V: Refine unsigned SAT_TRUNC testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,2/6] RISC-V: Refine unsigned SAT_SUB testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized [v1,1/6] RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized - - - - --- 2024-12-08 Li, Pan2 New
[v1,2/2] RISC-V: Refactor the testcases for rvv binop and cmp [v1,1/2] RISC-V: Fix incorrect optimization options passing to binop and cmp - - - - --- 2024-12-06 Li, Pan2 New
[v1,1/2] RISC-V: Fix incorrect optimization options passing to binop and cmp [v1,1/2] RISC-V: Fix incorrect optimization options passing to binop and cmp - - - - --- 2024-12-06 Li, Pan2 New
[v1] Match: Refactor the unsigned SAT_TRUNC match patterns [NFC] [v1] Match: Refactor the unsigned SAT_TRUNC match patterns [NFC] - - - - --- 2024-12-05 Li, Pan2 New
[v1] RISC-V: Add assert for insn operand out of range access [PR117878][NFC] [v1] RISC-V: Add assert for insn operand out of range access [PR117878][NFC] - - - - --- 2024-12-04 Li, Pan2 New
[v1,2/2] RISC-V: Refactor the testcases for bswap16-0 [v1,1/2] RISC-V: Fix incorrect optimization options passing to convert and unop - - - - --- 2024-12-04 Li, Pan2 New
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