Show patches with: Submitter = Kito Cheng       |    State = Action Required       |    Archived = No       |   240 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[committed] RISC-V: Add sifive_vector.h [committed] RISC-V: Add sifive_vector.h - - - - --- 2025-01-20 Kito Cheng New
[v4] RISC-V: Fix code gen for reduction with length 0 [PR118182] [v4] RISC-V: Fix code gen for reduction with length 0 [PR118182] - - - - --- 2025-01-06 Kito Cheng New
[v3] RISC-V: Fix code gen for reduction with length 0 [PR118182] [v3] RISC-V: Fix code gen for reduction with length 0 [PR118182] - - - - --- 2024-12-23 Kito Cheng New
[v2] RISC-V: Fix code gen for reduction with length 0 [PR118182] [v2] RISC-V: Fix code gen for reduction with length 0 [PR118182] - - - - --- 2024-12-23 Kito Cheng New
RISC-V: Fix code gen for reduction with length 0 [PR118182] RISC-V: Fix code gen for reduction with length 0 [PR118182] - - - - --- 2024-12-23 Kito Cheng New
RISC-V: Move fortran testcase to gfortran.target RISC-V: Move fortran testcase to gfortran.target - - - - --- 2024-12-23 Kito Cheng New
[v2,5/5] RISC-V: Add new constraint R for register even-odd pairs New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - - - --- 2024-12-12 Kito Cheng New
[v2,4/5] RISC-V: Implment N modifier for printing the register number rather than the register name New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - - - --- 2024-12-12 Kito Cheng New
[v2,3/5] RISC-V: Rename internal operand modifier N to n New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - - - --- 2024-12-12 Kito Cheng New
[v2,2/5] RISC-V: Add cr and cf constraint New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - - - --- 2024-12-12 Kito Cheng New
[v2,1/5] RISC-V: Rename constraint c0* to k0* New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - - - --- 2024-12-12 Kito Cheng New
[5/5] RISC-V: Add new constraint R for register even-odd pairs New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - - - --- 2024-12-09 Kito Cheng New
[4/5] RISC-V: Implment N modifier for printing the register number rather than the register name New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - - - --- 2024-12-09 Kito Cheng New
[3/5] RISC-V Rename internal operand modifier N to n New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - - - --- 2024-12-09 Kito Cheng New
[2/5] RISC-V: Add cr and cf constraint New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - - - --- 2024-12-09 Kito Cheng New
[1/5] RISC-V: Rename constraint c0* to k0* New Asm Constraints and Modifiers - RVC, Raw Encodings, Pairs - - - - --- 2024-12-09 Kito Cheng New
[committed] RISC-V: Add const to function_shape::get_name [NFC] [committed] RISC-V: Add const to function_shape::get_name [NFC] - - - - --- 2024-12-05 Kito Cheng New
[v3] RISC-V: Add --with-cmodel configure option [v3] RISC-V: Add --with-cmodel configure option - - - - --- 2024-12-05 Kito Cheng New
[2/2] RISC-V: Use dynamic shadow offset [1/2] asan: Support dynamic shadow offset - - - - --- 2024-11-15 Kito Cheng New
[1/2] asan: Support dynamic shadow offset [1/2] asan: Support dynamic shadow offset - - - - --- 2024-11-15 Kito Cheng New
[4/4] libsanitizer: update test libsanitizer: merge from upstream - - - - --- 2024-11-07 Kito Cheng New
[3/4] libsanitizer: Improve FrameIsInternal libsanitizer: merge from upstream - - - - --- 2024-11-07 Kito Cheng New
[2/4] libsanitizer: Apply local patches libsanitizer: merge from upstream - - - - --- 2024-11-07 Kito Cheng New
[1/4] libsanitizer: merge from upstream (61a6439f35b6de28) libsanitizer: merge from upstream - - - - --- 2024-11-07 Kito Cheng New
RISC-V: Add missing mode_idx for vrol and vror RISC-V: Add missing mode_idx for vrol and vror - - - - --- 2024-08-27 Kito Cheng New
[v4] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_… [v4] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_… - - - - --- 2024-07-23 Kito Cheng New
[v3] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_… [v3] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_… - - - - --- 2024-07-22 Kito Cheng New
[v2] RISC-V: Implement __init_riscv_features_bits, __riscv_feature_bits, and __riscv_vendor_feature… [v2] RISC-V: Implement __init_riscv_features_bits, __riscv_feature_bits, and __riscv_vendor_feature… - - - - --- 2024-07-18 Kito Cheng New
RISC-V: Implement __init_riscv_features_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits RISC-V: Implement __init_riscv_features_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits - - - - --- 2024-07-16 Kito Cheng New
[committed] RISC-V: Add SiFive extensions, xsfvcp and xsfcease [committed] RISC-V: Add SiFive extensions, xsfvcp and xsfcease - - - - --- 2024-07-12 Kito Cheng New
[committed] RISC-V: Fix typos in code or comment [NFC] [committed] RISC-V: Fix typos in code or comment [NFC] - - - - --- 2024-05-10 Kito Cheng New
[13] RISC-V: Fix vsetvli local eliminate [PR114747] [13] RISC-V: Fix vsetvli local eliminate [PR114747] - - - - --- 2024-05-07 Kito Cheng New
[13] RISC-V: Fix recursive vsetvli checking [PR114172] [13] RISC-V: Fix recursive vsetvli checking [PR114172] - - - - --- 2024-04-24 Kito Cheng New
wwwdocs: gcc-14: Add RISC-V changes wwwdocs: gcc-14: Add RISC-V changes 1 - 1 - --- 2024-04-10 Kito Cheng New
RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64 RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64 - - 1 - --- 2024-02-28 Kito Cheng New
[committed] RISC-V: Fix *sge<u>_<X:mode><GPR:mode> pattern [committed] RISC-V: Fix *sge<u>_<X:mode><GPR:mode> pattern - - - - --- 2024-02-16 Kito Cheng New
RISC-V: Add new option -march=help to print all supported extensions RISC-V: Add new option -march=help to print all supported extensions - - 1 - --- 2024-02-15 Kito Cheng New
[committed] RISC-V: Update testcase due to message update [committed] RISC-V: Update testcase due to message update - - - - --- 2024-01-19 Kito Cheng New
[v2] RISC-V: Documnet the list of supported extensions [v2] RISC-V: Documnet the list of supported extensions - - - - --- 2024-01-19 Kito Cheng New
RISC-V: Tweak the wording for the sorry message RISC-V: Tweak the wording for the sorry message - - - - --- 2024-01-19 Kito Cheng New
RISC-V: Documnet the list of supported extensions RISC-V: Documnet the list of supported extensions - - - - --- 2024-01-11 Kito Cheng New
[5/5] RISC-V: Document the syntax of -march RISC-V: Relax the -march string for accept any order - - - - --- 2024-01-08 Kito Cheng New
[4/5] RISC-V: Update testsuite due to -march string relaxation RISC-V: Relax the -march string for accept any order - - - - --- 2024-01-08 Kito Cheng New
[3/5] RISC-V: Remove unused function in riscv_subset_list [NFC] RISC-V: Relax the -march string for accept any order - - - - --- 2024-01-08 Kito Cheng New
[2/5] RISC-V: Relax the -march string for accept any order RISC-V: Relax the -march string for accept any order - - - - --- 2024-01-08 Kito Cheng New
[1/5] RISC-V: Extract part parsing base ISA logic into a standalone function [NFC] RISC-V: Relax the -march string for accept any order - - - - --- 2024-01-08 Kito Cheng New
[committed] RISC-V: Fix testsuite [committed] RISC-V: Fix testsuite - - - - --- 2024-01-08 Kito Cheng New
[committed] RISC-V: Clean up unused variable [NFC] [committed] RISC-V: Clean up unused variable [NFC] - - - - --- 2024-01-05 Kito Cheng New
[committed] RISC-V: Clean up testsuite for multi-lib testing [NFC] [committed] RISC-V: Clean up testsuite for multi-lib testing [NFC] - - - - --- 2024-01-05 Kito Cheng New
RISC-V: Fix misaligned stack offset for interrupt function RISC-V: Fix misaligned stack offset for interrupt function - - - - --- 2023-12-25 Kito Cheng New
RISC-V: Check if zcd conflicts with zcmt and zcmp RISC-V: Check if zcd conflicts with zcmt and zcmp - - - - --- 2023-12-04 Kito Cheng New
[committed] RISC-V: Add sifive-x280 to -mcpu [committed] RISC-V: Add sifive-x280 to -mcpu - - - - --- 2023-12-04 Kito Cheng New
[committed] RISC-V: Refactor riscv_implied_info_t to make it able to handle conditional implication… [committed] RISC-V: Refactor riscv_implied_info_t to make it able to handle conditional implication… - - - - --- 2023-12-04 Kito Cheng New
[committed] RISC-V: Refine riscv_subset_list::parse [NFC] [committed] RISC-V: Refine riscv_subset_list::parse [NFC] - - - - --- 2023-12-04 Kito Cheng New
[committed] RISC-V: Fix mismatched new delete for unique_ptr [committed] RISC-V: Fix mismatched new delete for unique_ptr - - - - --- 2023-11-18 Kito Cheng New
[v2] RISC-V: Implement target attribute [v2] RISC-V: Implement target attribute - - 1 - --- 2023-11-14 Kito Cheng New
RISC-V: Save/restore ra register correctly [PR112478] RISC-V: Save/restore ra register correctly [PR112478] - - 1 1 --- 2023-11-14 Kito Cheng New
[v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512. [v2] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512. - - - - --- 2023-10-12 Kito Cheng New
[committed] RISC-V: Add TARGET_MIN_VLEN_OPTS to fix the build [committed] RISC-V: Add TARGET_MIN_VLEN_OPTS to fix the build - - - - --- 2023-10-11 Kito Cheng New
[v2,4/4] RISC-V: Implement target attribute RISC-V target attribute - - - - --- 2023-10-10 Kito Cheng New
[v2,3/4] RISC-V: Extend riscv_subset_list, preparatory for target attribute support RISC-V target attribute - - - - --- 2023-10-10 Kito Cheng New
[v2,2/4] RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC] RISC-V target attribute - - - - --- 2023-10-10 Kito Cheng New
[v2,1/4] options: Define TARGET_<NAME>_P and TARGET_<NAME>_OPTS_P macro for Mask and InverseMask RISC-V target attribute - - - - --- 2023-10-10 Kito Cheng New
[v1,4/4] RISC-V: Implement target attribute [v1,1/4] options: Define TARGET_<NAME>_P and TARGET_<NAME>_OPTS_P macro for Mask and InverseMask - - - - --- 2023-10-03 Kito Cheng New
[v1,3/4] RISC-V: Extend riscv_subset_list, preparatory for target attribute support [v1,1/4] options: Define TARGET_<NAME>_P and TARGET_<NAME>_OPTS_P macro for Mask and InverseMask - - - - --- 2023-10-03 Kito Cheng New
[v1,2/4] RISC-V: Refactor riscv_option_override and riscv_convert_vector_bits. [NFC] [v1,1/4] options: Define TARGET_<NAME>_P and TARGET_<NAME>_OPTS_P macro for Mask and InverseMask - - - - --- 2023-10-03 Kito Cheng New
[v1,1/4] options: Define TARGET_<NAME>_P and TARGET_<NAME>_OPTS_P macro for Mask and InverseMask [v1,1/4] options: Define TARGET_<NAME>_P and TARGET_<NAME>_OPTS_P macro for Mask and InverseMask - - - - --- 2023-10-03 Kito Cheng New
RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512. RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512. - - - - --- 2023-10-03 Kito Cheng New
options: Prevent multidimensional arrays options: Prevent multidimensional arrays - - - - --- 2023-10-02 Kito Cheng New
RISC-V: Emit .note.GNU-stack for non-linux target as well RISC-V: Emit .note.GNU-stack for non-linux target as well - - - - --- 2023-08-31 Kito Cheng New
RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFC RISC-V: Return machine_mode rather than opt_machine_mode for get_mask_mode, NFC - - - - --- 2023-07-31 Kito Cheng New
doc: Add doc for RISC-V Operand Modifiers doc: Add doc for RISC-V Operand Modifiers - - - - --- 2023-07-10 Kito Cheng New
RISC-V: Handle rouding mode correctly on zfinx RISC-V: Handle rouding mode correctly on zfinx - - - - --- 2023-07-05 Kito Cheng New
RISC-V: Basic VLS code gen for RISC-V RISC-V: Basic VLS code gen for RISC-V - - - - --- 2023-05-30 Kito Cheng New
RISC-V: Add missing torture-init and torture-finish for rvv.exp RISC-V: Add missing torture-init and torture-finish for rvv.exp - - - - --- 2023-05-22 Kito Cheng New
[committed] RISC-V: Fix wrong select_kind in riscv_compute_multilib [committed] RISC-V: Fix wrong select_kind in riscv_compute_multilib - - - - --- 2023-05-16 Kito Cheng New
[committed] RISC-V: Pull out function call with side effect from gcc_assert. [committed] RISC-V: Pull out function call with side effect from gcc_assert. - - - - --- 2023-05-13 Kito Cheng New
RISC-V: Improve vector_insn_info::dump for LMUL and policy RISC-V: Improve vector_insn_info::dump for LMUL and policy - - - - --- 2023-05-12 Kito Cheng New
[committed,v4] RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] [committed,v4] RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] - - - - --- 2023-05-12 Kito Cheng New
[committed] RISC-V: Suppress unused parameter warning in riscv-common.cc [committed] RISC-V: Suppress unused parameter warning in riscv-common.cc - - - - --- 2023-05-12 Kito Cheng New
[committed,v2] RISC-V: Support const series vector for RVV auto-vectorization [committed,v2] RISC-V: Support const series vector for RVV auto-vectorization - - - - --- 2023-05-11 Kito Cheng New
[committed] RISC-V: Improve portability of testcases [committed] RISC-V: Improve portability of testcases - - - - --- 2023-05-08 Kito Cheng New
[committed] RISC-V: Factor out vector manager code in vsetvli insertion pass. [NFC] [committed] RISC-V: Factor out vector manager code in vsetvli insertion pass. [NFC] - - - - --- 2023-05-08 Kito Cheng New
[v2] RISC-V: Handle multi-lib path correclty for linux [v2] RISC-V: Handle multi-lib path correclty for linux - - - - --- 2023-05-04 Kito Cheng New
RISC-V: Handle multi-lib path correclty for linux RISC-V: Handle multi-lib path correclty for linux - - - - --- 2023-05-04 Kito Cheng New
[v2] Docs: Add vector register constarint for asm operands [v2] Docs: Add vector register constarint for asm operands - - - - --- 2023-04-27 Kito Cheng New
Docs: Add vector register constarint for asm operands Docs: Add vector register constarint for asm operands - - - - --- 2023-04-27 Kito Cheng New
[committed,v2] RISC-V: Add local user vsetvl instruction elimination [PR109547] [committed,v2] RISC-V: Add local user vsetvl instruction elimination [PR109547] - - - - --- 2023-04-21 Kito Cheng New
[committed,v2] RISC-V: Handle multi-lib path correclty for linux [DRAFT] [committed,v2] RISC-V: Handle multi-lib path correclty for linux [DRAFT] - - - - --- 2023-04-21 Kito Cheng New
[committed] RISC-V: Fix riscv/arch-19.c with different ISA spec version [committed] RISC-V: Fix riscv/arch-19.c with different ISA spec version - - - - --- 2023-04-20 Kito Cheng New
[committed] RISC-V: Fix simplify_ior_optimization.c on rv32 [committed] RISC-V: Fix simplify_ior_optimization.c on rv32 - - - - --- 2023-04-20 Kito Cheng New
[committed,v2] gcc-13: Add release note for RISC-V [committed,v2] gcc-13: Add release note for RISC-V - - - - --- 2023-04-20 Kito Cheng New
[wwwdocs] gcc-13: Add release note for RISC-V [wwwdocs] gcc-13: Add release note for RISC-V - - - - --- 2023-04-19 Kito Cheng New
Docs: Add doc for RISC-V vector intrinsics Docs: Add doc for RISC-V vector intrinsics - - - - --- 2023-04-18 Kito Cheng New
[committed] RISC-V: Fix testsuite fail on RV32 [committed] RISC-V: Fix testsuite fail on RV32 - - - - --- 2023-04-17 Kito Cheng New
[committed] RISC-V: Fix missing file dependency in RISC-V back-end [PR109328] [committed] RISC-V: Fix missing file dependency in RISC-V back-end [PR109328] - - - - --- 2023-03-31 Kito Cheng New
RISC-V: Define __riscv_v_intrinsic [PR109312] RISC-V: Define __riscv_v_intrinsic [PR109312] - - - - --- 2023-03-28 Kito Cheng New
[committed] RISC-V: Make the test condition more strict for gcc.target/riscv/_Float16-zhinxmin-1.c [committed] RISC-V: Make the test condition more strict for gcc.target/riscv/_Float16-zhinxmin-1.c - - - - --- 2023-02-22 Kito Cheng New
[committed] RISC-V: prefetch.* only take base register with zero-offset for the address [committed] RISC-V: prefetch.* only take base register with zero-offset for the address - - - - --- 2023-02-20 Kito Cheng New
RISC-V: Handle vlenb correctly in unwinding RISC-V: Handle vlenb correctly in unwinding - - - - --- 2023-02-12 Kito Cheng New
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