Show patches with: State = Action Required       |    Archived = No       |   136179 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[avr] ad PR117726: Tweak 32-bit logical shifts of 25...30 for -Oz [avr] ad PR117726: Tweak 32-bit logical shifts of 25...30 for -Oz - - - - --- 2025-01-22 Georg-Johann Lay New
ipa-cp: Perform operations in the appropriate types (PR 118097) ipa-cp: Perform operations in the appropriate types (PR 118097) - - - - --- 2025-01-22 Martin Jambor New
[5/5] LoongArch: Remove "b 3f" instruction if unneeded LoongArch: Atomic operation clean-up and micro-optimization - - - - --- 2025-01-22 Xi Ruoyao New
[4/5] LoongArch: Don't emit overly-restrictive barrier for LL-SC loops LoongArch: Atomic operation clean-up and micro-optimization - - - - --- 2025-01-22 Xi Ruoyao New
[3/5] LoongArch: Allow using bstrins for masking the address in atomic_test_and_set LoongArch: Atomic operation clean-up and micro-optimization - - - - --- 2025-01-22 Xi Ruoyao New
[2/5] LoongArch: Don't use "+" for atomic_{load, store} "m" constraint LoongArch: Atomic operation clean-up and micro-optimization - - - - --- 2025-01-22 Xi Ruoyao New
[1/5] LoongArch: (NFC) Remove atomic_optab and use amop instead LoongArch: Atomic operation clean-up and micro-optimization - - - - --- 2025-01-22 Xi Ruoyao New
[fortran] PR96087 - [12/13/14/15 Regression] ICE in gfc_get_symbol_decl, at fortran/trans-decl.c:15… [fortran] PR96087 - [12/13/14/15 Regression] ICE in gfc_get_symbol_decl, at fortran/trans-decl.c:15… - - - - --- 2025-01-22 Paul Richard Thomas New
[pushed:,r15-7126] jit: fix startup on aarch64 [pushed:,r15-7126] jit: fix startup on aarch64 - - - - --- 2025-01-22 David Malcolm New
LoongArch: Fix invalid subregs in xorsign [PR118501] LoongArch: Fix invalid subregs in xorsign [PR118501] - - - - --- 2025-01-22 Xi Ruoyao New
[PUSHED] s390: Fix arch15 machine string for binutils [PUSHED] s390: Fix arch15 machine string for binutils - - - - --- 2025-01-22 Stefan Schulze Frielinghaus New
[pushed] aarch64: Fix aarch64_write_sysregdi predicate [pushed] aarch64: Fix aarch64_write_sysregdi predicate - - - - --- 2025-01-22 Richard Sandiford New
[3/3] aarch64: Avoid redundant writes to FPMR [1/3] aarch64: Allow FPMR source values to be zero - - - - --- 2025-01-22 Richard Sandiford New
[2/3] aarch64: Fix memory cost for FPM_REGNUM [1/3] aarch64: Allow FPMR source values to be zero - - - - --- 2025-01-22 Richard Sandiford New
[1/3] aarch64: Allow FPMR source values to be zero [1/3] aarch64: Allow FPMR source values to be zero - - - - --- 2025-01-22 Richard Sandiford New
c++/modules: Fix exporting temploid friends in header units [PR118582] c++/modules: Fix exporting temploid friends in header units [PR118582] - - - - --- 2025-01-22 Nathaniel Shead New
[avr,applied] Add tests for LRA's PR118591 [avr,applied] Add tests for LRA's PR118591 - - - - --- 2025-01-22 Georg-Johann Lay New
[v4] arm: [MVE intrinsics] Avoid warnings when floating-point is not supported [PR 117814] [v4] arm: [MVE intrinsics] Avoid warnings when floating-point is not supported [PR 117814] - - - - --- 2025-01-22 Christophe Lyon New
builtins: Store unspecified value to *exp for inf/nan [PR114877] builtins: Store unspecified value to *exp for inf/nan [PR114877] - - - - --- 2025-01-22 Jakub Jelinek New
RISC-V: Disable two-source permutes for now [PR117173]. RISC-V: Disable two-source permutes for now [PR117173]. - - - - --- 2025-01-22 Robin Dapp New
i386: Append -march=x86-64-v3 to AVX10.2/512 VNNI testcases i386: Append -march=x86-64-v3 to AVX10.2/512 VNNI testcases - - - - --- 2025-01-22 Haochen Jiang New
[2/2] LoongArch: Partially fix code regression from r15-7062 LoongArch: Bitwise and shift reassoc fixes - - - - --- 2025-01-22 Xi Ruoyao New
[1/2] LoongArch: Fix wrong code with <optab>_alsl_reversesi_extended LoongArch: Bitwise and shift reassoc fixes - - - - --- 2025-01-22 Xi Ruoyao New
PR tree-optimization/95801 - infer non-zero for integral division RHS. PR tree-optimization/95801 - infer non-zero for integral division RHS. - - - - --- 2025-01-21 Andrew MacLeod New
[committed] testsuite: Require int32plus for test case pr117546.c [committed] testsuite: Require int32plus for test case pr117546.c - - - - --- 2025-01-21 Dimitar Dimitrov New
[committed] libphobos: Add MIPS64 implementation of fiber_switchContext [PR118584] [committed] libphobos: Add MIPS64 implementation of fiber_switchContext [PR118584] - - - - --- 2025-01-21 Iain Buclaw New
[GCC-12/13,committed] d: Fix ICE in build_deref, at d/d-codegen.cc:1650 [PR111650] Untitled series #441271 - - - - --- 2025-01-21 Iain Buclaw New
c++, v2: Introduce append_ctor_to_tree_vector c++, v2: Introduce append_ctor_to_tree_vector - - - - --- 2025-01-21 Jakub Jelinek New
c++: Improve cp_parser_objc_messsage_args compile time c++: Improve cp_parser_objc_messsage_args compile time - - - - --- 2025-01-21 Jakub Jelinek New
[committed] testsuite: Add testcase for already fixed PR [PR118560] [committed] testsuite: Add testcase for already fixed PR [PR118560] - - - - --- 2025-01-21 Jakub Jelinek New
c++: Handle CWG2867 even in namespace scope structured bindings in header modules [PR115769] c++: Handle CWG2867 even in namespace scope structured bindings in header modules [PR115769] - - - - --- 2025-01-21 Jakub Jelinek New
c++: Introduce append_ctor_to_tree_vector c++: Introduce append_ctor_to_tree_vector - - - - --- 2025-01-21 Jakub Jelinek New
c++: Handle CPP_EMBED in cp_parser_objc_message_args [PR118586] c++: Handle CPP_EMBED in cp_parser_objc_message_args [PR118586] - - - - --- 2025-01-21 Jakub Jelinek New
vect: Force alignment peeling to vectorize more early break loops [PR118211]: update 'gcc.dg/vect/v… vect: Force alignment peeling to vectorize more early break loops [PR118211]: update 'gcc.dg/vect/v… - - - - --- 2025-01-21 Thomas Schwinge New
tree-optimization/118558 - fix alignment compute with VMAT_CONTIGUOUS_REVERSE tree-optimization/118558 - fix alignment compute with VMAT_CONTIGUOUS_REVERSE - - - - --- 2025-01-21 Richard Biener New
Honor dump options for C/C++ '-fdump-tree-original' Honor dump options for C/C++ '-fdump-tree-original' - - - - --- 2025-01-21 Thomas Schwinge New
[committed] Regenerate aarch64.opt.urls [committed] Regenerate aarch64.opt.urls - - - - --- 2025-01-21 Alfie Richards New
[v5] RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not get a non-zero imm… [v5] RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not get a non-zero imm… - - - - --- 2025-01-21 Jin Ma New
tree-optimization/118569 - LC SSA broken after unrolling tree-optimization/118569 - LC SSA broken after unrolling - - - - --- 2025-01-21 Richard Biener New
[v2] RISC-V: Enable and adjust the testsuite for XTheadVector. [v2] RISC-V: Enable and adjust the testsuite for XTheadVector. - - - - --- 2025-01-21 Jin Ma New
[v6] AArch64: Add LUTI ACLE for SVE2 [v6] AArch64: Add LUTI ACLE for SVE2 - - - - --- 2025-01-21 Saurabh Jha New
[13/13] i386: Omit "p" for packed in intrin name for FP8 convert Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[12/13] i386: Change mnemonics from VCVT[, T]NEBF162I[, U]BS to VCVT[, T]BF162I[, U]BS Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[11/13] i386: Change mnemonics from VCVTNEPH2[B, H]F8 to VCVTPH2[B, H]F8 Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[10/13] i386: Change mnemonics from VCVTNE2PH2[B, H]F8 to VCVT2PH2[B, H]F8 Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[09/13] i386: Change mnemonics from VCOMSBF16 to VCOMISBF16 Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[08/13] i386: Change mnemonics from V[GETEXP, FPCLASS]PBF16 to V[GETEXP.FPCLASS]BF16 Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[07/13] i386: Change mnemonics from V[RSQRT, SCALEF, SQRTNE]PBF16 to V[RSQRT.SCALEF.SQRT]BF16 Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[06/13] i386: Change mnemonics from V[GETMANT, REDUCENE, RNDSCALENE]PBF16 to V[GETMANT, REDUCE, RND… Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[05/13] i386: Change mnemonics from VMINMAXNEPBF16 to VMINMAXBF16 Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[04/13] i386: Change mnemonics from V[CMP, MAX, MIN]PBF16 to V[CMP, MAX, MIN]BF16 Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[03/13] i386: Change mnemonics from VF[, N]M[ADD, SUB][132, 213, 231]NEPBF16 to VF[, N]M[ADD, SUB][… Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[02/13] i386: Change mnemonics from V[ADDNE, DIVNE, MULNE, RCP, SUBNE]PBF16 to V[ADD, DIV, MUL, RCP… Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[01/13] i386: Enhance AMX tests Realign x86 GCC after Binutils change [PR118270] - - - - --- 2025-01-21 Haochen Jiang New
[to-be-committed,RISC-V,PR,target/116256] Fix incorrect return value for predicate [to-be-committed,RISC-V,PR,target/116256] Fix incorrect return value for predicate - - - - --- 2025-01-21 Jeff Law New
[GCC16/PATCH] combine: Better split point for `(and (not X))` [PR111949] [GCC16/PATCH] combine: Better split point for `(and (not X))` [PR111949] - - - - --- 2025-01-21 Andrew Pinski New
[2/2] RISC-V: Support RISC-V Profiles 23. RISC-V: Support RISC-V Profiles. - - - - --- 2025-01-21 Jiawei New
[v2,1/2] RISC-V: Support RISC-V Profiles 20/22. RISC-V: Support RISC-V Profiles. - - - - --- 2025-01-21 Jiawei New
[V5,2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - - - --- 2025-01-21 yulong New
[V5,1/2] RISC-V: Add intrinsics support for SiFive Xsfvcp extensions. RISC-V: Add intrinsics support and testcases for SiFive Xsfvcp extension. - - - - --- 2025-01-21 yulong New
[v3] c++: fix wrong-code with constexpr prvalue opt [PR118396] [v3] c++: fix wrong-code with constexpr prvalue opt [PR118396] - - 1 - --- 2025-01-20 Marek Polacek New
[GCC-12,committed] d: Fix failing test with 32-bit compiler [PR114434] [GCC-12,committed] d: Fix failing test with 32-bit compiler [PR114434] - - - - --- 2025-01-20 Iain Buclaw New
[pushed,PR118560,LRA] : Fix typo in checking secondary memory mode for the reg class [pushed,PR118560,LRA] : Fix typo in checking secondary memory mode for the reg class - - - - --- 2025-01-20 Vladimir Makarov New
[committed,PR,target/116256] Adjust expected output in a couple testcases [committed,PR,target/116256] Adjust expected output in a couple testcases - - - - --- 2025-01-20 Jeff Law New
[avr] Tweak some 16-bit shifts using MUL. [avr] Tweak some 16-bit shifts using MUL. - - - - --- 2025-01-20 Georg-Johann Lay New
[to-be-committed,PR,target/114442] Add reservations for all insn types to xiangshan-nanhu model [to-be-committed,PR,target/114442] Add reservations for all insn types to xiangshan-nanhu model - - - - --- 2025-01-20 Jeff Law New
[_Hashtable] Fix hash code cache usage [_Hashtable] Fix hash code cache usage - - - - --- 2025-01-20 François Dumont New
[committed] Fortran: improve error message for conflicting OpenMP clauses [PR107122] [committed] Fortran: improve error message for conflicting OpenMP clauses [PR107122] - - - - --- 2025-01-20 Harald Anlauf New
vect: Preserve OMP info for conditional stores [PR118384] vect: Preserve OMP info for conditional stores [PR118384] - - - - --- 2025-01-20 Richard Sandiford New
[pushed] aarch64: Fix invalid subregs in xorsign [PR118501] [pushed] aarch64: Fix invalid subregs in xorsign [PR118501] - - - - --- 2025-01-20 Richard Sandiford New
[to-be-committed,RISC-V,PR,target/116256] Fix latent regression in pattern to associate arithmetic … [to-be-committed,RISC-V,PR,target/116256] Fix latent regression in pattern to associate arithmetic … - - - - --- 2025-01-20 Jeff Law New
[committed] d: Fix failing test with 32-bit compiler [PR114434] [committed] d: Fix failing test with 32-bit compiler [PR114434] - - - - --- 2025-01-20 Iain Buclaw New
middle-end: use ncopies both when registering and reading masks [PR118273] middle-end: use ncopies both when registering and reading masks [PR118273] - - - - --- 2025-01-20 Tamar Christina New
[v5] AArch64: Add LUTI ACLE for SVE2 [v5] AArch64: Add LUTI ACLE for SVE2 - - - - --- 2025-01-20 Saurabh Jha New
tree-optimization/117875 - missed SLP vectorization tree-optimization/117875 - missed SLP vectorization - - - - --- 2025-01-20 Richard Biener New
tree-optimization/118552 - failed LC SSA update after unrolling tree-optimization/118552 - failed LC SSA update after unrolling - - - - --- 2025-01-20 Richard Biener New
c++/modules: Handle mismatching TYPE_CANONICAL when deduping partial specs [PR118101] c++/modules: Handle mismatching TYPE_CANONICAL when deduping partial specs [PR118101] - - - - --- 2025-01-20 Nathaniel Shead New
nvptx: Gracefully handle '-mptx=3.1' if neither sm_30 nor sm_35 multilib variant is built (was: nvp… nvptx: Gracefully handle '-mptx=3.1' if neither sm_30 nor sm_35 multilib variant is built (was: nvp… - - - - --- 2025-01-20 Thomas Schwinge New
[18/18] s390: Update vec_(load,store)_len(,_r) s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[17/18] s390: Vector shift: Add 128-bit integer support s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[16/18] s390: arch15: Vector maximum/minimum: Add 128-bit integer support s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[15/18] s390: arch15: Vector load positive: Add 128-bit integer support s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[14/18] s390: arch15: Vector compare: Add 128-bit integer support s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[13/18] s390: arch15: Vector devide/remainder s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[12/18] s390: arch15: Count leading/trailing zeros s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[11/18] s390: arch15: Vector generate element masks s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[10/18] s390: arch15: Vector eval s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[09/18] s390: arch15: Vector blend s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[08/18] s390: arch15: Bit deposit and extract s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[07/18] s390: arch15: Load indexed address s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[06/18] s390: arch15: New instruction variants supporting 128-bit integer s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[05/18] s390: arch15: Prepare for future builtins s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[04/18] s390: Bump __VEC__ and add 128-bit integer zvector types s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[03/18] s390: arch15: Prepare for a future architecture s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[02/18] s390: Sort definitions in vecintrin.h s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[01/18] s390: Stay scalar for TOINTVEC/tointvec s390: arch15: Prepare for a future architecture - - - - --- 2025-01-20 Stefan Schulze Frielinghaus New
[v2,2/2] LoongArch: Implement target pragma. [v2,1/2] LoongArch: Implement target attribute. - - - - --- 2025-01-20 Lulu Cheng New
[v2,1/2] LoongArch: Implement target attribute. [v2,1/2] LoongArch: Implement target attribute. - - - - --- 2025-01-20 Lulu Cheng New
[v2,0/2] Implement target attribute and pragma. - - - - --- 2025-01-20 Lulu Cheng New
[v1] RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688] [v1] RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688] - - - - --- 2025-01-20 Li, Pan2 New
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