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[V4,0/2] Separate PowerPC ISA bits from architecture bits set by -mcpu=<xxx>

Message ID ZzjbojlqLdZlef5u@cowardly-lion.the-meissners.org
Headers show
Series Separate PowerPC ISA bits from architecture bits set by -mcpu=<xxx> | expand

Message

Michael Meissner Nov. 16, 2024, 5:51 p.m. UTC
Peter Bergner asked me to reorganize my V3 patch that separates the
architecture bits (set via -mcpu=<xxx>) compared to the ISA bits that are based
on options.

Here is the beginning of the V3 patch for reference:

https://gcc.gnu.org/pipermail/gcc-patches/2024-November/668643.html

As Peter has suggested, I reworked the patch so the the bits where I rename the
target flags comes before the bit about separating the architecture bits.  I
also moved the -mcpu=future bits before the architecture bits as well.

There are 4 separate patch sets (that might have separate patches within the
patch sets).  Each of the patch sets is a logical entity.

The 4 patch sets are:

    1:	Rename the TARGET_<xxx> options so that they say TARGET_POWER5 instead
	of TARGET_POPCNTB.  In this patch set, TARGET_POWER5 is a macro that
	references TARGET_POPCNTB.  The 5 patches in this patch set rename each
	option in turn.

    2:	Add support for -mcpu=future.  Because the architecture mask support is
	in the 4th patch set, this patch set adds a dummy switch -mfuture.

    3:	Make -mvsx not internally set -mcpu=power7.  This has come up in
	several bugs.  This is independent of the other patches, and can be
	omitted if desired.

    4:	The last patch set now provides the separation between the architecture
	bits and the ISA bits.  It removes several of the dummy switches
	(-mpower10, -mpower11, -mfuture) that were added to support those
	processors, but users aren't supposed to use those options.

These patches are the 4th patch set in the series.  They depend on the
The first two patch sets being applied:

https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669067.html
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669099.html

There are two patches in this patch set:

    1:	This patch provides the basic infrastructure to have a separate set of
	architecture masks that is split from the ISA masks.  This patch also
	updates the code handling .machine selection and the target_clone
	attribute to use the architecture masks instead of the ISA masks.

    2:	This patch removes the -mpower8-internal, -mpower10, -mpower11, and
	-mfuture switches, since that support is now handled by the
	architecture masks.

I have built GCC with the patches in this patch set applied on both little and
big endian PowerPC systems and there were no regressions.  Can I apply these
patches to GCC 15?

Comments

Michael Meissner Dec. 4, 2024, 7:50 a.m. UTC | #1
Ping patches 1-2 to separate PowerPC ISA bits from architecture bits set by
-mcpu=<xxx>.

Message-ID <ZzjYrw3LdkkMbZ5y@cowardly-lion.the-meissners.org>

Explanation of the patch set:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669108.html

Patch #1, add rs6000 architecture masks:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669109.html

Patch #2, use architecture flags for defining _ARCH_PWR macros:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669110.html
Michael Meissner Jan. 9, 2025, 6:03 p.m. UTC | #2
Ping patches 1-2 to separate PowerPC ISA bits from architecture bits set by
-mcpu=<xxx>.

Message-ID <ZzjYrw3LdkkMbZ5y@cowardly-lion.the-meissners.org>

Explanation of the patch set:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669108.html

Patch #1, add rs6000 architecture masks:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669109.html

Patch #2, use architecture flags for defining _ARCH_PWR macros:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669110.html
Michael Meissner Jan. 23, 2025, 8:16 p.m. UTC | #3
Ping patches 1-2 to separate PowerPC ISA bits from architecture bits set by
-mcpu=<xxx>.

Message-ID <ZzjYrw3LdkkMbZ5y@cowardly-lion.the-meissners.org>

Explanation of the patch set:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669108.html

Patch #1, add rs6000 architecture masks:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669109.html

Patch #2, use architecture flags for defining _ARCH_PWR macros:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669110.html
Michael Meissner Feb. 13, 2025, 1 a.m. UTC | #4
Ping patches 1-2 to separate PowerPC ISA bits from architecture bits set by
-mcpu=<xxx>.

Note, I will be away on vacation from Tuesday February 25th through Friday
March 7th.  At this point of time, I do not anticipate bringing a laptop that I
can respond to emails on this account.

Message-ID <ZzjYrw3LdkkMbZ5y@cowardly-lion.the-meissners.org>

Explanation of the patch set:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669108.html

Patch #1, add rs6000 architecture masks:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669109.html

Patch #2, use architecture flags for defining _ARCH_PWR macros:
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669110.html