From patchwork Wed Oct 2 17:13:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1992115 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XJhHq1sRRz1xtY for ; Thu, 3 Oct 2024 03:14:31 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AEE323858CD1 for ; Wed, 2 Oct 2024 17:14:27 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id CE24D3858D29 for ; Wed, 2 Oct 2024 17:14:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CE24D3858D29 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CE24D3858D29 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1727889242; cv=none; b=mpmaDfrc+LvR7TAMQbfpZCvsUlKrSn83bEhirZ/LYzHcEUMlU6WN1DyZGBlov0x44HiBC7SJ3sPbFMzsZZKn9sLMDk35I/ez2SYaBTTfvmh4LYn0QrCUdDGKLJM91M08C+Y8mBmb0i8znOZsM8NtF3X7elKiRLKi0gVbrELVVL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1727889242; c=relaxed/simple; bh=r0saSxR+SxPTbFYW7GGkFEqJcexOTXcb41E0kyCjS7c=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=G8WgQoOfQsqscG062xVPvyLPgSd4N3regoHTbqAbN0jml8MVmiAJ7wIbGhAwQ7iRFWRzzDRWtCWOjxPgNtBZYA89DOIIuqYpAmgdpEhUMOumnrvj49VcFPMJHv1jv3xp8jFKrHBeBv4SqJkkTnleNXMYsdcNjTTOUfZgV4gwJQ4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0DCD4339; Wed, 2 Oct 2024 10:14:30 -0700 (PDT) Received: from e107157-lin.cambridge.arm.com (e107157-lin.cambridge.arm.com [10.2.78.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DC6A93F64C; Wed, 2 Oct 2024 10:13:59 -0700 (PDT) From: Andre Vieira To: gcc-patches@gcc.gnu.org Cc: richard.sandiford@arm.com, Andre Vieira Subject: [PATCH 0/2] aarch64: remove SVE2 requirement from SME and diagnose it as unsupported Date: Wed, 2 Oct 2024 18:13:37 +0100 Message-Id: <20241002171339.299940-1-andre.simoesdiasvieira@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch series removes the requirement of SVE2 for SME, so when a user passes +sme, SVE2 is not enabled as a result of that. We do this to be compliant with the ISA and behave in a compatible manner to other toolchains, to prevent unexpected behavior when switching between them. However, for the time being we diagnose the use of SME without SVE2 as unsupported, we suspect that the backend correctly enables and disables the right instructions given the options, but we believe that for certain codegen there are assumptions that SVE & SVE2 is present when using SME. Before we fully support this combination we should investigate these. The patch series also refactors the FCMA/COMPNUM/TARGET_COMPLEX feature to separate it from Armv8.3-A feature set. Andre Vieira (2) aarch64: Split FCMA feature bit from Armv8.3-A aarch64: remove SVE2 requirement from SME and diagnose it as unsupported Regression tested on aarch64-none-linux-gnu. OK for trunk? Andre Vieira (2): aarch64: Split FCMA feature bit from Armv8.3-A aarch64: remove SVE2 requirement from SME and diagnose it as unsupported gcc/config/aarch64/aarch64-arches.def | 2 +- gcc/config/aarch64/aarch64-option-extensions.def | 4 +++- gcc/config/aarch64/aarch64.cc | 4 ++++ gcc/config/aarch64/aarch64.h | 2 +- .../aarch64/sve/acle/general-c/binary_int_opt_single_n_2.c | 2 +- .../aarch64/sve/acle/general-c/binary_opt_single_n_2.c | 2 +- .../gcc.target/aarch64/sve/acle/general-c/binary_single_1.c | 2 +- .../gcc.target/aarch64/sve/acle/general-c/binaryxn_2.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/clamp_1.c | 2 +- .../aarch64/sve/acle/general-c/compare_scalar_count_1.c | 2 +- .../aarch64/sve/acle/general-c/shift_right_imm_narrowxn_1.c | 2 +- .../gcc.target/aarch64/sve/acle/general-c/storexn_1.c | 2 +- .../aarch64/sve/acle/general-c/ternary_qq_or_011_lane_1.c | 2 +- .../gcc.target/aarch64/sve/acle/general-c/unary_convertxn_1.c | 2 +- .../gcc.target/aarch64/sve/acle/general-c/unaryxn_1.c | 2 +- 15 files changed, 20 insertions(+), 14 deletions(-)