From dc67f47cffaa3ff7cf5dab837f4f5e2595355475 Mon Sep 17 00:00:00 2001
From: Nikolay Nikolaev <evrinoma@gmail.com>
Date: Sun, 22 Dec 2019 14:36:02 +0300
Subject: [PATCH] It's added support for ST95XXX chips . The following chipsets
have been tested for read, erase and write operations: [ STM95080 STM95160
STM95320 STM95640 STM95128 STM95256 STM95512 STM95M01 STM95M02 ]
The chipsets(except st95xxx with literal D) can't respond with RDID instruction and for this reason was added FEATURE_IDENTITY_MISSING feature. The feature works with "force" option and disable rdid checking during read operation.
Also It's emulates erase operation for chipsets which don't support it.
Known issue: It doesn't support chipset STM95040 because memory size lower then 1K and the chipset has special instruction set for read operation.
part 2 fix RDID ST95
Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com>
---
spi.h | 42 +++++++++++++++++++++---------------------
spi25.c | 10 +++++++---
2 files changed, 28 insertions(+), 24 deletions(-)
@@ -30,27 +30,27 @@
#define JEDEC_RDID_INSIZE 0x03
/* Some ST M95X model */
-#define ST_M95_RDID 0x83
-#define ST_M95_RDID_OUTSIZE 0x03
-#define ST_M95_RDID_INSIZE 0x03
-#define ST_M95_RDLS 0x83
-#define ST_M95_RDLS_OUTSIZE 0x03
-#define ST_M95_RDLS_INSIZE 0x01
-#define ST_M95_RDSR 0x05
-#define ST_M95_RDSR_OUTSIZE 0x01
-#define ST_M95_RDSR_INSIZE 0x01
-#define ST_M95_READ 0x03
-#define ST_M95_READ_OUTSIZE 0x03
-#define ST_M95_READ_INSIZE 0x03
-#define ST_M95_WREN 0x06
-#define ST_M95_WREN_OUTSIZE 0x01
-#define ST_M95_WREN_INSIZE 0x00
-#define ST_M95_WRITE 0x02
-#define ST_M95_WRITE_OUTSIZE 0x06
-#define ST_M95_WRITE_INSIZE 0x03
-#define ST_M95_WRID 0x82
-#define ST_M95_WRID_OUTSIZE 0x06
-#define ST_M95_WRID_INSIZE 0x00
+#define ST_M95_RDID 0x83
+/* #define ST_M95_RDID_OUTSIZE 0x01*/
+#define ST_M95_RDID_INSIZE 0x04 /* 24 bit address*/
+#define ST_M95_RDLS 0x83
+#define ST_M95_RDLS_OUTSIZE 0x03
+#define ST_M95_RDLS_INSIZE 0x01
+#define ST_M95_RDSR 0x05
+#define ST_M95_RDSR_OUTSIZE 0x01
+#define ST_M95_RDSR_INSIZE 0x01
+#define ST_M95_READ 0x03
+#define ST_M95_READ_OUTSIZE 0x03
+#define ST_M95_READ_INSIZE 0x03
+#define ST_M95_WREN 0x06
+#define ST_M95_WREN_OUTSIZE 0x01
+#define ST_M95_WREN_INSIZE 0x00
+#define ST_M95_WRITE 0x02
+#define ST_M95_WRITE_OUTSIZE 0x06
+#define ST_M95_WRITE_INSIZE 0x03
+#define ST_M95_WRID 0x82
+#define ST_M95_WRID_OUTSIZE 0x06
+#define ST_M95_WRID_INSIZE 0x00
/* Some Atmel AT25F* models have bit 3 as don't care bit in commands */
#define AT25F_RDID 0x15 /* 0x15 or 0x1d */
@@ -268,16 +268,20 @@ int probe_spi_st95(struct flashctx *flash)
{
//
static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
- unsigned char readarr[JEDEC_RDID_INSIZE];
+ unsigned char readarr[ST_M95_RDID_INSIZE];
uint32_t manufacture_id;
uint32_t model_id;
- spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr);
+ uint32_t rdid_outsize = ST_M95_RDID_INSIZE;
+ if (flash->chip->feature_bits & FEATURE_3_BYTE_ADDR_LEN)
+ rdid_outsize = JEDEC_RDID_INSIZE;
+
+ spi_send_command(flash, sizeof(cmd), rdid_outsize, cmd, readarr);
manufacture_id = readarr[0];
model_id = readarr[2];
- msg_ginfo("RDID[%s: manID 0x%02x, modID 0x%02x, L 0x%02x, M 0x%02x, H 0x%02x]\n", __func__, flash->chip->manufacture_id, flash->chip->model_id, readarr[0], readarr[1], readarr[2]);
+ msg_ginfo("RDID[%s: manID 0x%02x, modID 0x%02x, L 0x%02x, H 0x%02x]\n", __func__, flash->chip->manufacture_id, flash->chip->model_id, manufacture_id, model_id);
if (manufacture_id == flash->chip->manufacture_id && model_id == flash->chip->model_id)
return 1;
--
2.24.0