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[v1,0/6] Enable IPQ5424 USB support

Message ID 20241112091355.2028018-1-quic_varada@quicinc.com
Headers show
Series Enable IPQ5424 USB support | expand

Message

Varadarajan Narayanan Nov. 12, 2024, 9:13 a.m. UTC 
The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0
can connect to either of USB2.0 or USB3.0 phy and operate in the
respective mode.

Varadarajan Narayanan (6):
  dt-bindings: phy: qcom,qusb2: Document IPQ5424 compatible
  phy: qcom-qusb2: add QUSB2 support for IPQ5424
  dt-bindings: phy: qcom,qmp-usb: Add IPQ5424 USB3 PHY
  phy: qcom: qmp: Enable IPQ5424 support
  dt-bindings: usb: qcom,dwc3: Add IPQ5424 to USB DWC3 bindings
  arm64: dts: qcom: Add USB controller and phy nodes for IPQ5424

 .../bindings/phy/qcom,qusb2-phy.yaml          |   1 +
 .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml   |   2 +
 .../devicetree/bindings/usb/qcom,dwc3.yaml    |   1 +
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts   |  67 ++++++++
 arch/arm64/boot/dts/qcom/ipq5424.dtsi         | 153 ++++++++++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp-usb.c       |   3 +
 drivers/phy/qualcomm/phy-qcom-qusb2.c         |  28 ++++
 7 files changed, 255 insertions(+)


base-commit: 28955f4fa2823e39f1ecfb3a37a364563527afbc

Comments

Krishna Kurapati Nov. 12, 2024, 9:35 a.m. UTC | #1 
On 11/12/2024 2:43 PM, Varadarajan Narayanan wrote:
> The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0
> can connect to either of USB2.0 or USB3.0 phy and operate in the
> respective mode.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts |  67 +++++++++
>   arch/arm64/boot/dts/qcom/ipq5424.dtsi       | 153 ++++++++++++++++++++
>   2 files changed, 220 insertions(+)
> 

[...]

> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> index 5e219f900412..d8c045a311c2 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> @@ -233,6 +233,159 @@ intc: interrupt-controller@f200000 {
>   			msi-controller;
>   		};
>   
> +		qusb_phy_1: phy@71000 {
> +			compatible = "qcom,ipq5424-qusb2-phy";
> +			reg = <0 0x00071000 0 0x180>;
> +			#phy-cells = <0>;
> +
> +			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
> +				<&xo_board>;
> +			clock-names = "cfg_ahb", "ref";
> +
> +			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
> +			status = "disabled";
> +		};
> +
> +		usb2: usb2@1e00000 {
> +			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
> +			reg = <0 0x01ef8800 0 0x400>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +
> +			clocks = <&gcc GCC_USB1_MASTER_CLK>,
> +				 <&gcc GCC_USB1_SLEEP_CLK>,
> +				 <&gcc GCC_USB1_MOCK_UTMI_CLK>,
> +				 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
> +				 <&gcc GCC_CNOC_USB_CLK>;
> +
> +			clock-names = "core",
> +				      "sleep",
> +				      "mock_utmi",
> +				      "iface",
> +				      "cfg_noc";
> +
> +			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
> +					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
> +			assigned-clock-rates = <200000000>,
> +					       <24000000>; > +

Shouldn't this be 19.2MHz ?

> +			interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "pwr_event",
> +					  "qusb2_phy",
> +					  "dm_hs_phy_irq",
> +					  "dp_hs_phy_irq";
> +

Please check the hs_phy_irq as well and add it if its present.

> +			resets = <&gcc GCC_USB1_BCR>;
> +			qcom,select-utmi-as-pipe-clk;
> +			status = "disabled";
> +
> +			dwc_1: usb@1e00000 {
> +				compatible = "snps,dwc3";
> +				reg = <0 0x01e00000 0 0xe000>;
> +				clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
> +				clock-names = "ref";

Another clock in dwc3 node ?

> +				interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
> +				phys = <&qusb_phy_1>;
> +				phy-names = "usb2-phy";
> +				tx-fifo-resize;
> +				snps,is-utmi-l1-suspend;
> +				snps,hird-threshold = /bits/ 8 <0x0>;
> +				snps,dis_u2_susphy_quirk;
> +				snps,dis_u3_susphy_quirk;
> +			};
> +		};
> +
> +		qusb_phy_0: phy@7b000 {
> +			compatible = "qcom,ipq5424-qusb2-phy";
> +			reg = <0 0x0007b000 0 0x180>;
> +			#phy-cells = <0>;
> +
> +			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> +				<&xo_board>;
> +			clock-names = "cfg_ahb", "ref";
> +
> +			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> +			status = "disabled";
> +		};
> +
> +		ssphy_0: phy@7d000 {
> +			compatible = "qcom,ipq5424-qmp-usb3-phy";
> +			reg = <0 0x0007d000 0 0xa00>;
> +			#phy-cells = <0>;
> +
> +			clocks = <&gcc GCC_USB0_AUX_CLK>,
> +				 <&xo_board>,
> +				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> +				 <&gcc GCC_USB0_PIPE_CLK>;
> +			clock-names = "aux",
> +				      "ref",
> +				      "cfg_ahb",
> +				      "pipe";
> +
> +			resets = <&gcc GCC_USB0_PHY_BCR>,
> +				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
> +			reset-names = "phy",
> +				      "phy_phy";
> +
> +			#clock-cells = <0>;
> +			clock-output-names = "usb0_pipe_clk";
> +
> +			status = "disabled";
> +		};
> +
> +		usb3: usb3@8a00000 {
> +			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
> +			reg = <0 0x08af8800 0 0x400>;
> +
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +
> +			clocks = <&gcc GCC_USB0_MASTER_CLK>,
> +				 <&gcc GCC_USB0_SLEEP_CLK>,
> +				 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
> +				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> +				 <&gcc GCC_CNOC_USB_CLK>;
> +
> +			clock-names = "core",
> +				      "sleep",
> +				      "mock_utmi",
> +				      "iface",
> +				      "cfg_noc";
> +
> +			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> +					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +			assigned-clock-rates = <200000000>,
> +					       <24000000>;
> +

same comment as above, isn't this supposed to be 19.2MHz ?

> +			interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "pwr_event",
> +					  "qusb2_phy";
> +

DP/ DM interrupts ?

> +			resets = <&gcc GCC_USB_BCR>;
> +			status = "disabled";
> +
> +			dwc_0: usb@8a00000 {
> +				compatible = "snps,dwc3";
> +				reg = <0 0x08a00000 0 0xcd00>;
> +				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +				clock-names = "ref";
> +				interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> +				phys = <&qusb_phy_0>, <&ssphy_0>;
> +				phy-names = "usb2-phy", "usb3-phy";
> +				tx-fifo-resize;
> +				snps,is-utmi-l1-suspend;
> +				snps,hird-threshold = /bits/ 8 <0x0>;
> +				snps,dis_u2_susphy_quirk;
> +				snps,dis_u3_susphy_quirk;

Disable u1/u2 entry as well please.

Regards,
Krishna,

> +			};
> +		};
> +
>   		timer@f420000 {
>   			compatible = "arm,armv7-timer-mem";
>   			reg = <0 0xf420000 0 0x1000>;
Varadarajan Narayanan Nov. 12, 2024, 12:05 p.m. UTC | #2 
On Tue, Nov 12, 2024 at 03:05:57PM +0530, Krishna Kurapati wrote:
>
>
> On 11/12/2024 2:43 PM, Varadarajan Narayanan wrote:
> > The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0
> > can connect to either of USB2.0 or USB3.0 phy and operate in the
> > respective mode.
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> >   arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts |  67 +++++++++
> >   arch/arm64/boot/dts/qcom/ipq5424.dtsi       | 153 ++++++++++++++++++++
> >   2 files changed, 220 insertions(+)
> >
>
> [...]
>
> > diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> > index 5e219f900412..d8c045a311c2 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> > @@ -233,6 +233,159 @@ intc: interrupt-controller@f200000 {
> >   			msi-controller;
> >   		};
> > +		qusb_phy_1: phy@71000 {
> > +			compatible = "qcom,ipq5424-qusb2-phy";
> > +			reg = <0 0x00071000 0 0x180>;
> > +			#phy-cells = <0>;
> > +
> > +			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
> > +				<&xo_board>;
> > +			clock-names = "cfg_ahb", "ref";
> > +
> > +			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
> > +			status = "disabled";
> > +		};
> > +
> > +		usb2: usb2@1e00000 {
> > +			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
> > +			reg = <0 0x01ef8800 0 0x400>;
> > +			#address-cells = <2>;
> > +			#size-cells = <2>;
> > +			ranges;
> > +
> > +			clocks = <&gcc GCC_USB1_MASTER_CLK>,
> > +				 <&gcc GCC_USB1_SLEEP_CLK>,
> > +				 <&gcc GCC_USB1_MOCK_UTMI_CLK>,
> > +				 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
> > +				 <&gcc GCC_CNOC_USB_CLK>;
> > +
> > +			clock-names = "core",
> > +				      "sleep",
> > +				      "mock_utmi",
> > +				      "iface",
> > +				      "cfg_noc";
> > +
> > +			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
> > +					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
> > +			assigned-clock-rates = <200000000>,
> > +					       <24000000>; > +
>
> Shouldn't this be 19.2MHz ?

XO is 24MHz in this SoC.

> > +			interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> > +					      <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> > +					      <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
> > +					      <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "pwr_event",
> > +					  "qusb2_phy",
> > +					  "dm_hs_phy_irq",
> > +					  "dp_hs_phy_irq";
> > +
>
> Please check the hs_phy_irq as well and add it if its present.

Will add.

> > +			resets = <&gcc GCC_USB1_BCR>;
> > +			qcom,select-utmi-as-pipe-clk;
> > +			status = "disabled";
> > +
> > +			dwc_1: usb@1e00000 {
> > +				compatible = "snps,dwc3";
> > +				reg = <0 0x01e00000 0 0xe000>;
> > +				clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
> > +				clock-names = "ref";
>
> Another clock in dwc3 node ?
>
> > +				interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
> > +				phys = <&qusb_phy_1>;
> > +				phy-names = "usb2-phy";
> > +				tx-fifo-resize;
> > +				snps,is-utmi-l1-suspend;
> > +				snps,hird-threshold = /bits/ 8 <0x0>;
> > +				snps,dis_u2_susphy_quirk;
> > +				snps,dis_u3_susphy_quirk;
> > +			};
> > +		};
> > +
> > +		qusb_phy_0: phy@7b000 {
> > +			compatible = "qcom,ipq5424-qusb2-phy";
> > +			reg = <0 0x0007b000 0 0x180>;
> > +			#phy-cells = <0>;
> > +
> > +			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > +				<&xo_board>;
> > +			clock-names = "cfg_ahb", "ref";
> > +
> > +			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> > +			status = "disabled";
> > +		};
> > +
> > +		ssphy_0: phy@7d000 {
> > +			compatible = "qcom,ipq5424-qmp-usb3-phy";
> > +			reg = <0 0x0007d000 0 0xa00>;
> > +			#phy-cells = <0>;
> > +
> > +			clocks = <&gcc GCC_USB0_AUX_CLK>,
> > +				 <&xo_board>,
> > +				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > +				 <&gcc GCC_USB0_PIPE_CLK>;
> > +			clock-names = "aux",
> > +				      "ref",
> > +				      "cfg_ahb",
> > +				      "pipe";
> > +
> > +			resets = <&gcc GCC_USB0_PHY_BCR>,
> > +				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
> > +			reset-names = "phy",
> > +				      "phy_phy";
> > +
> > +			#clock-cells = <0>;
> > +			clock-output-names = "usb0_pipe_clk";
> > +
> > +			status = "disabled";
> > +		};
> > +
> > +		usb3: usb3@8a00000 {
> > +			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
> > +			reg = <0 0x08af8800 0 0x400>;
> > +
> > +			#address-cells = <2>;
> > +			#size-cells = <2>;
> > +			ranges;
> > +
> > +			clocks = <&gcc GCC_USB0_MASTER_CLK>,
> > +				 <&gcc GCC_USB0_SLEEP_CLK>,
> > +				 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
> > +				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > +				 <&gcc GCC_CNOC_USB_CLK>;
> > +
> > +			clock-names = "core",
> > +				      "sleep",
> > +				      "mock_utmi",
> > +				      "iface",
> > +				      "cfg_noc";
> > +
> > +			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> > +					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > +			assigned-clock-rates = <200000000>,
> > +					       <24000000>;
> > +
>
> same comment as above, isn't this supposed to be 19.2MHz ?

XO is 24MHz in this SoC.

> > +			interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
> > +					      <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "pwr_event",
> > +					  "qusb2_phy";
> > +
>
> DP/ DM interrupts ?

Will add.

> > +			resets = <&gcc GCC_USB_BCR>;
> > +			status = "disabled";
> > +
> > +			dwc_0: usb@8a00000 {
> > +				compatible = "snps,dwc3";
> > +				reg = <0 0x08a00000 0 0xcd00>;
> > +				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > +				clock-names = "ref";
> > +				interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> > +				phys = <&qusb_phy_0>, <&ssphy_0>;
> > +				phy-names = "usb2-phy", "usb3-phy";
> > +				tx-fifo-resize;
> > +				snps,is-utmi-l1-suspend;
> > +				snps,hird-threshold = /bits/ 8 <0x0>;
> > +				snps,dis_u2_susphy_quirk;
> > +				snps,dis_u3_susphy_quirk;
>
> Disable u1/u2 entry as well please.

Will add.

Thanks
Varada
Dmitry Baryshkov Nov. 12, 2024, 1:44 p.m. UTC | #3 
On Tue, Nov 12, 2024 at 02:43:51PM +0530, Varadarajan Narayanan wrote:
> Add the phy init sequence for the Super Speed ports found
> on IPQ5424.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
>  drivers/phy/qualcomm/phy-qcom-qusb2.c | 28 +++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index c52655a383ce..4513f0c81c50 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> @@ -151,6 +151,21 @@ static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
>  	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),
>  };
>  
> +static const struct qusb2_phy_init_tbl ipq5424_init_tbl[] = {
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x00),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC3),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
> +	QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80),
> +	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),

Lowercase hex numbers please. LGTM otherwise.

> +};
> +
>  static const unsigned int ipq6018_regs_layout[] = {
>  	[QUSB2PHY_PLL_STATUS]              = 0x38,
>  	[QUSB2PHY_PORT_TUNE1]              = 0x80,
> @@ -331,6 +346,16 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
>  	.autoresume_en   = BIT(0),
>  };
>  
> +static const struct qusb2_phy_cfg ipq5424_phy_cfg = {
> +	.tbl            = ipq5424_init_tbl,
> +	.tbl_num        = ARRAY_SIZE(ipq5424_init_tbl),
> +	.regs           = ipq6018_regs_layout,
> +
> +	.disable_ctrl   = POWER_DOWN,
> +	.mask_core_ready = PLL_LOCKED,
> +	.autoresume_en   = BIT(0),
> +};
> +
>  static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
>  	.tbl		= qusb2_v2_init_tbl,
>  	.tbl_num	= ARRAY_SIZE(qusb2_v2_init_tbl),
> @@ -905,6 +930,9 @@ static const struct phy_ops qusb2_phy_gen_ops = {
>  
>  static const struct of_device_id qusb2_phy_of_match_table[] = {
>  	{
> +		.compatible	= "qcom,ipq5424-qusb2-phy",
> +		.data		= &ipq5424_phy_cfg,
> +	}, {
>  		.compatible	= "qcom,ipq6018-qusb2-phy",
>  		.data		= &ipq6018_phy_cfg,
>  	}, {
> -- 
> 2.34.1
>
Dmitry Baryshkov Nov. 12, 2024, 1:45 p.m. UTC | #4 
On Tue, Nov 12, 2024 at 02:43:53PM +0530, Varadarajan Narayanan wrote:
> Enable QMP USB3 phy support for IPQ5424 SoC.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 +++
>  1 file changed, 3 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Varadarajan Narayanan Nov. 13, 2024, 7:01 a.m. UTC | #5 
On Tue, Nov 12, 2024 at 05:35:13PM +0530, Varadarajan Narayanan wrote:
> On Tue, Nov 12, 2024 at 03:05:57PM +0530, Krishna Kurapati wrote:
> >
> >
> > On 11/12/2024 2:43 PM, Varadarajan Narayanan wrote:
> > > The IPQ5424 SoC has both USB2.0 and USB3.0 controllers. The USB3.0
> > > can connect to either of USB2.0 or USB3.0 phy and operate in the
> > > respective mode.
> > >
> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > ---
> > >   arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts |  67 +++++++++
> > >   arch/arm64/boot/dts/qcom/ipq5424.dtsi       | 153 ++++++++++++++++++++
> > >   2 files changed, 220 insertions(+)
> > >
> >
> > [...]
> >
> > > diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> > > index 5e219f900412..d8c045a311c2 100644
> > > --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> > > @@ -233,6 +233,159 @@ intc: interrupt-controller@f200000 {
> > >   			msi-controller;
> > >   		};
> > > +		qusb_phy_1: phy@71000 {
> > > +			compatible = "qcom,ipq5424-qusb2-phy";
> > > +			reg = <0 0x00071000 0 0x180>;
> > > +			#phy-cells = <0>;
> > > +
> > > +			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
> > > +				<&xo_board>;
> > > +			clock-names = "cfg_ahb", "ref";
> > > +
> > > +			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
> > > +			status = "disabled";
> > > +		};
> > > +
> > > +		usb2: usb2@1e00000 {
> > > +			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
> > > +			reg = <0 0x01ef8800 0 0x400>;
> > > +			#address-cells = <2>;
> > > +			#size-cells = <2>;
> > > +			ranges;
> > > +
> > > +			clocks = <&gcc GCC_USB1_MASTER_CLK>,
> > > +				 <&gcc GCC_USB1_SLEEP_CLK>,
> > > +				 <&gcc GCC_USB1_MOCK_UTMI_CLK>,
> > > +				 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
> > > +				 <&gcc GCC_CNOC_USB_CLK>;
> > > +
> > > +			clock-names = "core",
> > > +				      "sleep",
> > > +				      "mock_utmi",
> > > +				      "iface",
> > > +				      "cfg_noc";
> > > +
> > > +			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
> > > +					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
> > > +			assigned-clock-rates = <200000000>,
> > > +					       <24000000>; > +
> >
> > Shouldn't this be 19.2MHz ?
>
> XO is 24MHz in this SoC.
>
> > > +			interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> > > +					      <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> > > +					      <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
> > > +					      <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
> > > +			interrupt-names = "pwr_event",
> > > +					  "qusb2_phy",
> > > +					  "dm_hs_phy_irq",
> > > +					  "dp_hs_phy_irq";
> > > +
> >
> > Please check the hs_phy_irq as well and add it if its present.
>
> Will add.

Checked with HW team, there is no hs_phy_irq in this case.

> > > +			resets = <&gcc GCC_USB1_BCR>;
> > > +			qcom,select-utmi-as-pipe-clk;
> > > +			status = "disabled";
> > > +
> > > +			dwc_1: usb@1e00000 {
> > > +				compatible = "snps,dwc3";
> > > +				reg = <0 0x01e00000 0 0xe000>;
> > > +				clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
> > > +				clock-names = "ref";
> >
> > Another clock in dwc3 node ?

Not sure if I understand the above comment. Per bindings [1] a
clock entry is expected in this node.

1 - https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/usb/snps,dwc3.yaml#n57

Thanks
Varada

> > > +				interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
> > > +				phys = <&qusb_phy_1>;
> > > +				phy-names = "usb2-phy";
> > > +				tx-fifo-resize;
> > > +				snps,is-utmi-l1-suspend;
> > > +				snps,hird-threshold = /bits/ 8 <0x0>;
> > > +				snps,dis_u2_susphy_quirk;
> > > +				snps,dis_u3_susphy_quirk;
> > > +			};
> > > +		};
> > > +
> > > +		qusb_phy_0: phy@7b000 {
> > > +			compatible = "qcom,ipq5424-qusb2-phy";
> > > +			reg = <0 0x0007b000 0 0x180>;
> > > +			#phy-cells = <0>;
> > > +
> > > +			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > > +				<&xo_board>;
> > > +			clock-names = "cfg_ahb", "ref";
> > > +
> > > +			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> > > +			status = "disabled";
> > > +		};
> > > +
> > > +		ssphy_0: phy@7d000 {
> > > +			compatible = "qcom,ipq5424-qmp-usb3-phy";
> > > +			reg = <0 0x0007d000 0 0xa00>;
> > > +			#phy-cells = <0>;
> > > +
> > > +			clocks = <&gcc GCC_USB0_AUX_CLK>,
> > > +				 <&xo_board>,
> > > +				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > > +				 <&gcc GCC_USB0_PIPE_CLK>;
> > > +			clock-names = "aux",
> > > +				      "ref",
> > > +				      "cfg_ahb",
> > > +				      "pipe";
> > > +
> > > +			resets = <&gcc GCC_USB0_PHY_BCR>,
> > > +				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
> > > +			reset-names = "phy",
> > > +				      "phy_phy";
> > > +
> > > +			#clock-cells = <0>;
> > > +			clock-output-names = "usb0_pipe_clk";
> > > +
> > > +			status = "disabled";
> > > +		};
> > > +
> > > +		usb3: usb3@8a00000 {
> > > +			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
> > > +			reg = <0 0x08af8800 0 0x400>;
> > > +
> > > +			#address-cells = <2>;
> > > +			#size-cells = <2>;
> > > +			ranges;
> > > +
> > > +			clocks = <&gcc GCC_USB0_MASTER_CLK>,
> > > +				 <&gcc GCC_USB0_SLEEP_CLK>,
> > > +				 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
> > > +				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > > +				 <&gcc GCC_CNOC_USB_CLK>;
> > > +
> > > +			clock-names = "core",
> > > +				      "sleep",
> > > +				      "mock_utmi",
> > > +				      "iface",
> > > +				      "cfg_noc";
> > > +
> > > +			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> > > +					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > > +			assigned-clock-rates = <200000000>,
> > > +					       <24000000>;
> > > +
> >
> > same comment as above, isn't this supposed to be 19.2MHz ?
>
> XO is 24MHz in this SoC.
>
> > > +			interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
> > > +					      <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
> > > +			interrupt-names = "pwr_event",
> > > +					  "qusb2_phy";
> > > +
> >
> > DP/ DM interrupts ?
>
> Will add.
>
> > > +			resets = <&gcc GCC_USB_BCR>;
> > > +			status = "disabled";
> > > +
> > > +			dwc_0: usb@8a00000 {
> > > +				compatible = "snps,dwc3";
> > > +				reg = <0 0x08a00000 0 0xcd00>;
> > > +				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > > +				clock-names = "ref";
> > > +				interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> > > +				phys = <&qusb_phy_0>, <&ssphy_0>;
> > > +				phy-names = "usb2-phy", "usb3-phy";
> > > +				tx-fifo-resize;
> > > +				snps,is-utmi-l1-suspend;
> > > +				snps,hird-threshold = /bits/ 8 <0x0>;
> > > +				snps,dis_u2_susphy_quirk;
> > > +				snps,dis_u3_susphy_quirk;
> >
> > Disable u1/u2 entry as well please.
>
> Will add.
>
> Thanks
> Varada
>