Message ID | 1255278912-8042-8-git-send-email-Joakim.Tjernlund@transmode.se (mailing list archive) |
---|---|
State | Superseded, archived |
Delegated to: | Benjamin Herrenschmidt |
Headers | show |
On Sun, 2009-10-11 at 18:35 +0200, Joakim Tjernlund wrote: > 8xx has not had WRITETHRU due to lack of bits in the pte. > After the recent rewrite of the 8xx TLB code, there are > two bits left. Use one of them to WRITETHRU. > > Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE? _PAGE_FILE can already overwrite other bits as it's only set when !present, and should pretty much always be 0x2 I think I've replaced _PAGE_EXEC with _PAGE_SPECIAL already upstream since _PAGE_EXEC is unused on 8xx. Cheers, Ben. > --- > arch/powerpc/include/asm/pte-8xx.h | 5 +++-- > arch/powerpc/kernel/head_8xx.S | 8 ++++++++ > 2 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h > index f23cd15..9349d83 100644 > --- a/arch/powerpc/include/asm/pte-8xx.h > +++ b/arch/powerpc/include/asm/pte-8xx.h > @@ -34,12 +34,13 @@ > #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ > #define _PAGE_DIRTY 0x0100 /* C: page changed */ > > -/* These 3 software bits must be masked out when the entry is loaded > - * into the TLB, 2 SW bits left. > +/* These 4 software bits must be masked out when the entry is loaded > + * into the TLB, 1 SW bit left(0x0080). > */ > #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ > #define _PAGE_GUARDED 0x0010 /* software: guarded access */ > #define _PAGE_ACCESSED 0x0020 /* software: page referenced */ > +#define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */ > > /* Setting any bits in the nibble with the follow two controls will > * require a TLB exception handler change. It is assumed unused bits > diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S > index 371b606..db5207e 100644 > --- a/arch/powerpc/kernel/head_8xx.S > +++ b/arch/powerpc/kernel/head_8xx.S > @@ -422,6 +422,10 @@ DataStoreTLBMiss: > * above. > */ > rlwimi r11, r10, 0, 27, 27 > + /* Insert the WriteThru flag into the TWC from the Linux PTE. > + * It is bit 25 in the Linux PTE and bit 30 in the TWC > + */ > + rlwimi r11, r10, 32-5, 30, 30 > DO_8xx_CPU6(0x3b80, r3) > mtspr SPRN_MD_TWC, r11 > > @@ -559,6 +563,10 @@ DARFix: /* Return from dcbx instruction bug workaround, r10 holds value of DAR * > * It is bit 27 of both the Linux PTE and the TWC > */ > rlwimi r11, r10, 0, 27, 27 > + /* Insert the WriteThru flag into the TWC from the Linux PTE. > + * It is bit 25 in the Linux PTE and bit 30 in the TWC > + */ > + rlwimi r11, r10, 32-5, 30, 30 > DO_8xx_CPU6(0x3b80, r3) > mtspr SPRN_MD_TWC, r11 > mfspr r11, SPRN_MD_TWC /* get the pte address again */
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote on 11/10/2009 23:26:27: > > On Sun, 2009-10-11 at 18:35 +0200, Joakim Tjernlund wrote: > > 8xx has not had WRITETHRU due to lack of bits in the pte. > > After the recent rewrite of the 8xx TLB code, there are > > two bits left. Use one of them to WRITETHRU. > > > > Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE? > > _PAGE_FILE can already overwrite other bits as it's only set > when !present, and should pretty much always be 0x2 OK. > > I think I've replaced _PAGE_EXEC with _PAGE_SPECIAL already > upstream since _PAGE_EXEC is unused on 8xx. What is page SPECIAL anyway?
On Mon, 2009-10-12 at 00:21 +0200, Joakim Tjernlund wrote: > > I think I've replaced _PAGE_EXEC with _PAGE_SPECIAL already > > upstream since _PAGE_EXEC is unused on 8xx. > > What is page SPECIAL anyway? It's used on newer kernels to indicates PTEs that map something that isn't backed by a struct page (ie, not memory) Cheers, Ben.
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h index f23cd15..9349d83 100644 --- a/arch/powerpc/include/asm/pte-8xx.h +++ b/arch/powerpc/include/asm/pte-8xx.h @@ -34,12 +34,13 @@ #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ #define _PAGE_DIRTY 0x0100 /* C: page changed */ -/* These 3 software bits must be masked out when the entry is loaded - * into the TLB, 2 SW bits left. +/* These 4 software bits must be masked out when the entry is loaded + * into the TLB, 1 SW bit left(0x0080). */ #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ #define _PAGE_GUARDED 0x0010 /* software: guarded access */ #define _PAGE_ACCESSED 0x0020 /* software: page referenced */ +#define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */ /* Setting any bits in the nibble with the follow two controls will * require a TLB exception handler change. It is assumed unused bits diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 371b606..db5207e 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -422,6 +422,10 @@ DataStoreTLBMiss: * above. */ rlwimi r11, r10, 0, 27, 27 + /* Insert the WriteThru flag into the TWC from the Linux PTE. + * It is bit 25 in the Linux PTE and bit 30 in the TWC + */ + rlwimi r11, r10, 32-5, 30, 30 DO_8xx_CPU6(0x3b80, r3) mtspr SPRN_MD_TWC, r11 @@ -559,6 +563,10 @@ DARFix: /* Return from dcbx instruction bug workaround, r10 holds value of DAR * * It is bit 27 of both the Linux PTE and the TWC */ rlwimi r11, r10, 0, 27, 27 + /* Insert the WriteThru flag into the TWC from the Linux PTE. + * It is bit 25 in the Linux PTE and bit 30 in the TWC + */ + rlwimi r11, r10, 32-5, 30, 30 DO_8xx_CPU6(0x3b80, r3) mtspr SPRN_MD_TWC, r11 mfspr r11, SPRN_MD_TWC /* get the pte address again */