Message ID | OF490DC464.F75531A6-ONC1257640.002AC41C-C1257640.002D2820@transmode.se (mailing list archive) |
---|---|
State | Superseded, archived |
Headers | show |
> hmm, yes. You do get this and mysterious SEGV if you hit the but so does > other bugs too so this is probably due to missing invalidation. > > I suspect that something like below will fix the problem and > is the "correct" fix(untested, not even compiled): Ok but do we also still have to worry about the "unpopulated" TLB entries and invalidate them somehow when populating ? Cheers, Ben.
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote on 29/09/2009 10:16:38: > > > > hmm, yes. You do get this and mysterious SEGV if you hit the but so does > > other bugs too so this is probably due to missing invalidation. > > > > I suspect that something like below will fix the problem and > > is the "correct" fix(untested, not even compiled): > > Ok but do we also still have to worry about the "unpopulated" TLB > entries and invalidate them somehow when populating ? No, this patch is to not populate the MMU with invalid entries at all. Hopefully you can remove those invalidate 8xx TLBs hacks you currently have. Jocke
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 52ff8c5..f579a11 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -428,7 +428,7 @@ DataStoreTLBMiss: * set. All other Linux PTE bits control the behavior * of the MMU. */ -2: li r11, 0x00f0 + li r11, 0x00f0 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x3d80, r3) mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ @@ -441,7 +441,23 @@ DataStoreTLBMiss: lwz r3, 8(r0) #endif rfi +2: + /* Copy 20 msb from MD_EPN to DAR since the dcxx instructions fails + * to update DAR when they cause a DTLB Miss. + */ + mfspr r11, SPRN_MD_EPN + mfspr r10, SPRN_DAR + rlwimi r10, r11, 0, 0, 19 + mtspr SPRN_DAR, r10 + mfspr r10, SPRN_M_TW /* Restore registers */ + lwz r11, 0(r0) + mtcr r11 + lwz r11, 4(r0) +#ifdef CONFIG_8xx_CPU6 + lwz r3, 8(r0) +#endif + b DataAccess /* This is an instruction TLB error on the MPC8xx. This could be due * to many reasons, such as executing guarded memory or illegal instruction * addresses. There is nothing to do but handle a big time error fault.