diff mbox

[v2,2/4] zynq_slcr: Add links to the CPUs

Message ID 85f8fdbc83b3a0e1d1aaf7cbc79bf4a79df0851c.1349308835.git.peter.crosthwaite@xilinx.com
State New
Headers show

Commit Message

Peter A. G. Crosthwaite Oct. 4, 2012, 12:16 a.m. UTC 
From: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>

The SLCR needs to be able to reset the CPUs, so link the CPUs to the slcr.

Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
---

 hw/xilinx_zynq.c |   11 +++++++++++
 hw/zynq_slcr.c   |    9 +++++++++
 2 files changed, 20 insertions(+), 0 deletions(-)

Comments

Peter Maydell Oct. 9, 2012, 11:45 a.m. UTC | #1 
On 4 October 2012 01:16, Peter Crosthwaite
<peter.crosthwaite@petalogix.com> wrote:
> From: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
>
> The SLCR needs to be able to reset the CPUs, so link the CPUs to the slcr.
>
> Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>

I think your patch 4/4 is the wrong approach to reset, so I'm not
going to review this one particularly (beyond the obvious that if
we need this it should be done globally, not specifically to Zynq).

-- PMM
diff mbox

Patch

diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index 22a2bc5..fc81521 100644
--- a/hw/xilinx_zynq.c
+++ b/hw/xilinx_zynq.c
@@ -100,6 +100,10 @@  static void zynq_init(ram_addr_t ram_size, const char *boot_device,
         }
         irqp = arm_pic_init_cpu(cpus[n]);
         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
+        /* FIXME: handle this somewhere central */
+        object_property_add_child(container_get(qdev_get_machine(),
+                                  "/unattached"), g_strdup_printf("cpu[%d]", n),
+                                  OBJECT(cpus[n]), NULL);
     }
 
     /* max 2GB ram */
@@ -128,6 +132,13 @@  static void zynq_init(ram_addr_t ram_size, const char *boot_device,
 
     dev = qdev_create(NULL, "xilinx,zynq_slcr");
     qdev_init_nofail(dev);
+    Error *errp = NULL;
+    object_property_set_link(OBJECT(dev), OBJECT(cpus[0]), "cpu0", &errp);
+    assert_no_error(errp);
+    if (smp_cpus > 1) {
+        object_property_set_link(OBJECT(dev), OBJECT(cpus[1]), "cpu1", NULL);
+        assert_no_error(errp);
+    }
     sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xF8000000);
 
     dev = qdev_create(NULL, "a9mpcore_priv");
diff --git a/hw/zynq_slcr.c b/hw/zynq_slcr.c
index 4f97575..468fb0e 100644
--- a/hw/zynq_slcr.c
+++ b/hw/zynq_slcr.c
@@ -19,6 +19,8 @@ 
 #include "sysbus.h"
 #include "sysemu.h"
 
+#define NUM_CPUS 2
+
 #ifdef ZYNQ_ARM_SLCR_ERR_DEBUG
 #define DB_PRINT(...) do { \
     fprintf(stderr,  ": %s: ", __func__); \
@@ -118,6 +120,8 @@  typedef struct {
     SysBusDevice busdev;
     MemoryRegion iomem;
 
+    ARMCPU *cpus[NUM_CPUS];
+
     union {
         struct {
             uint16_t scl;
@@ -496,6 +500,11 @@  static int zynq_slcr_init(SysBusDevice *dev)
     memory_region_init_io(&s->iomem, &slcr_ops, s, "slcr", 0x1000);
     sysbus_init_mmio(dev, &s->iomem);
 
+    object_property_add_link(OBJECT(dev), "cpu0", TYPE_ARM_CPU,
+                             (Object **) &s->cpus[0], NULL);
+    object_property_add_link(OBJECT(dev), "cpu1", TYPE_ARM_CPU,
+                             (Object **) &s->cpus[1], NULL);
+
     return 0;
 }