diff mbox

powerpc/85xx: Fix pci base address error for p2020rdb-pc in dts

Message ID 1342146455-27729-2-git-send-email-b29983@freescale.com (mailing list archive)
State Accepted, archived
Commit 771e6089e3638ea1e06700a9dc4660cd678e35bb
Delegated to: Kumar Gala
Headers show

Commit Message

tang yuantian July 13, 2012, 2:27 a.m. UTC
From: Tang Yuantian <Yuantian.Tang@freescale.com>

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
 arch/powerpc/boot/dts/p2020rdb-pc_32b.dts |    4 ++--
 arch/powerpc/boot/dts/p2020rdb-pc_36b.dts |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

Comments

Kumar Gala July 13, 2012, 1:55 p.m. UTC | #1
On Jul 12, 2012, at 9:27 PM, <b29983@freescale.com> <b29983@freescale.com> wrote:

> From: Tang Yuantian <Yuantian.Tang@freescale.com>
> 
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> ---
> arch/powerpc/boot/dts/p2020rdb-pc_32b.dts |    4 ++--
> arch/powerpc/boot/dts/p2020rdb-pc_36b.dts |    4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)

applied to next

- k
diff mbox

Patch

diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
index 852e5b2..57573bd 100644
--- a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
@@ -56,7 +56,7 @@ 
 		ranges = <0x0 0x0 0xffe00000 0x100000>;
 	};
 
-	pci0: pcie@ffe08000 {
+	pci2: pcie@ffe08000 {
 		reg = <0 0xffe08000 0 0x1000>;
 		status = "disabled";
 	};
@@ -76,7 +76,7 @@ 
 		};
 	};
 
-	pci2: pcie@ffe0a000 {
+	pci0: pcie@ffe0a000 {
 		reg = <0 0xffe0a000 0 0x1000>;
 		ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
 			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
index b5a56ca..470247e 100644
--- a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
@@ -56,7 +56,7 @@ 
 		ranges = <0x0 0xf 0xffe00000 0x100000>;
 	};
 
-	pci0: pcie@fffe08000 {
+	pci2: pcie@fffe08000 {
 		reg = <0xf 0xffe08000 0 0x1000>;
 		status = "disabled";
 	};
@@ -76,7 +76,7 @@ 
 		};
 	};
 
-	pci2: pcie@fffe0a000 {
+	pci0: pcie@fffe0a000 {
 		reg = <0xf 0xffe0a000 0 0x1000>;
 		ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;