| Message ID | 20240923093016.66437-9-shentey@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | E500 Cleanup | expand |
On Mon, 23 Sep 2024, Bernhard Beschow wrote: > The CCSR space is just a container which is meant to be covered by platform > device memory regions. However, QEMU only implements a subset of these devices. > Add some logging to see which devices a guest attempts to access. An aleternative solution for a similar problem is this: https://patchew.org/QEMU/20240520101007.A25A34E602E@zero.eik.bme.hu/ I don't know if that would be simpler for this device as well. Regards, BALATON Zoltan > Signed-off-by: Bernhard Beschow <shentey@gmail.com> > --- > hw/ppc/ppce500_ccsr.c | 33 +++++++++++++++++++++++++++++++-- > hw/ppc/trace-events | 3 +++ > 2 files changed, 34 insertions(+), 2 deletions(-) > > diff --git a/hw/ppc/ppce500_ccsr.c b/hw/ppc/ppce500_ccsr.c > index 191a9ceec3..28942b2348 100644 > --- a/hw/ppc/ppce500_ccsr.c > +++ b/hw/ppc/ppce500_ccsr.c > @@ -15,14 +15,43 @@ > */ > > #include "qemu/osdep.h" > +#include "qemu/log.h" > #include "e500-ccsr.h" > +#include "trace.h" > + > +static uint64_t ppce500_ccsr_io_read(void *opaque, hwaddr addr, unsigned size) > +{ > + uint64_t value = 0; > + > + trace_ppce500_ccsr_io_read(addr, value, size); > + qemu_log_mask(LOG_UNIMP, > + "%s: unimplemented [0x%" HWADDR_PRIx "] -> 0\n", > + __func__, addr); > + > + return value; > +} > + > +static void ppce500_ccsr_io_write(void *opaque, hwaddr addr, uint64_t value, > + unsigned size) > +{ > + trace_ppce500_ccsr_io_write(addr, value, size); > + qemu_log_mask(LOG_UNIMP, > + "%s: unimplemented [0x%" HWADDR_PRIx "] <- 0x%" PRIx32 "\n", > + __func__, addr, (uint32_t)value); > +} > + > +static const MemoryRegionOps ppce500_ccsr_ops = { > + .read = ppce500_ccsr_io_read, > + .write = ppce500_ccsr_io_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > +}; > > static void e500_ccsr_init(Object *obj) > { > PPCE500CCSRState *ccsr = CCSR(obj); > > - memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", > - MPC8544_CCSRBAR_SIZE); > + memory_region_init_io(&ccsr->ccsr_space, obj, &ppce500_ccsr_ops, obj, > + "e500-ccsr", MPC8544_CCSRBAR_SIZE); > sysbus_init_mmio(SYS_BUS_DEVICE(ccsr), &ccsr->ccsr_space); > } > > diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events > index 1f125ce841..ca4c231c9f 100644 > --- a/hw/ppc/trace-events > +++ b/hw/ppc/trace-events > @@ -143,6 +143,9 @@ ppc_irq_cpu(const char *action) "%s" > ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x" > ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x" > > +ppce500_ccsr_io_read(uint32_t index, uint32_t val, uint8_t size) "[0x%" PRIx32 "] -> 0x%08x (size: 0x%" PRIu8 ")" > +ppce500_ccsr_io_write(uint32_t index, uint32_t val, uint8_t size) "[0x%" PRIx32 "] <- 0x%08x (size: 0x%" PRIu8 ")" > + > # prep_systemio.c > prep_systemio_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x" > prep_systemio_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x" >
Am 24. September 2024 10:15:43 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>: >On Mon, 23 Sep 2024, Bernhard Beschow wrote: >> The CCSR space is just a container which is meant to be covered by platform >> device memory regions. However, QEMU only implements a subset of these devices. >> Add some logging to see which devices a guest attempts to access. > >An aleternative solution for a similar problem is this: >https://patchew.org/QEMU/20240520101007.A25A34E602E@zero.eik.bme.hu/ >I don't know if that would be simpler for this device as well. That was my first approach but I didn't like that `-d unimp` causes unrelated logging. With tracing one can be very targeted. Best regards, Bernhard > >Regards, >BALATON Zoltan > >> Signed-off-by: Bernhard Beschow <shentey@gmail.com> >> --- >> hw/ppc/ppce500_ccsr.c | 33 +++++++++++++++++++++++++++++++-- >> hw/ppc/trace-events | 3 +++ >> 2 files changed, 34 insertions(+), 2 deletions(-) >> >> diff --git a/hw/ppc/ppce500_ccsr.c b/hw/ppc/ppce500_ccsr.c >> index 191a9ceec3..28942b2348 100644 >> --- a/hw/ppc/ppce500_ccsr.c >> +++ b/hw/ppc/ppce500_ccsr.c >> @@ -15,14 +15,43 @@ >> */ >> >> #include "qemu/osdep.h" >> +#include "qemu/log.h" >> #include "e500-ccsr.h" >> +#include "trace.h" >> + >> +static uint64_t ppce500_ccsr_io_read(void *opaque, hwaddr addr, unsigned size) >> +{ >> + uint64_t value = 0; >> + >> + trace_ppce500_ccsr_io_read(addr, value, size); >> + qemu_log_mask(LOG_UNIMP, >> + "%s: unimplemented [0x%" HWADDR_PRIx "] -> 0\n", >> + __func__, addr); >> + >> + return value; >> +} >> + >> +static void ppce500_ccsr_io_write(void *opaque, hwaddr addr, uint64_t value, >> + unsigned size) >> +{ >> + trace_ppce500_ccsr_io_write(addr, value, size); >> + qemu_log_mask(LOG_UNIMP, >> + "%s: unimplemented [0x%" HWADDR_PRIx "] <- 0x%" PRIx32 "\n", >> + __func__, addr, (uint32_t)value); >> +} >> + >> +static const MemoryRegionOps ppce500_ccsr_ops = { >> + .read = ppce500_ccsr_io_read, >> + .write = ppce500_ccsr_io_write, >> + .endianness = DEVICE_NATIVE_ENDIAN, >> +}; >> >> static void e500_ccsr_init(Object *obj) >> { >> PPCE500CCSRState *ccsr = CCSR(obj); >> >> - memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", >> - MPC8544_CCSRBAR_SIZE); >> + memory_region_init_io(&ccsr->ccsr_space, obj, &ppce500_ccsr_ops, obj, >> + "e500-ccsr", MPC8544_CCSRBAR_SIZE); >> sysbus_init_mmio(SYS_BUS_DEVICE(ccsr), &ccsr->ccsr_space); >> } >> >> diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events >> index 1f125ce841..ca4c231c9f 100644 >> --- a/hw/ppc/trace-events >> +++ b/hw/ppc/trace-events >> @@ -143,6 +143,9 @@ ppc_irq_cpu(const char *action) "%s" >> ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x" >> ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x" >> >> +ppce500_ccsr_io_read(uint32_t index, uint32_t val, uint8_t size) "[0x%" PRIx32 "] -> 0x%08x (size: 0x%" PRIu8 ")" >> +ppce500_ccsr_io_write(uint32_t index, uint32_t val, uint8_t size) "[0x%" PRIx32 "] <- 0x%08x (size: 0x%" PRIu8 ")" >> + >> # prep_systemio.c >> prep_systemio_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x" >> prep_systemio_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x" >>
diff --git a/hw/ppc/ppce500_ccsr.c b/hw/ppc/ppce500_ccsr.c index 191a9ceec3..28942b2348 100644 --- a/hw/ppc/ppce500_ccsr.c +++ b/hw/ppc/ppce500_ccsr.c @@ -15,14 +15,43 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "e500-ccsr.h" +#include "trace.h" + +static uint64_t ppce500_ccsr_io_read(void *opaque, hwaddr addr, unsigned size) +{ + uint64_t value = 0; + + trace_ppce500_ccsr_io_read(addr, value, size); + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented [0x%" HWADDR_PRIx "] -> 0\n", + __func__, addr); + + return value; +} + +static void ppce500_ccsr_io_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + trace_ppce500_ccsr_io_write(addr, value, size); + qemu_log_mask(LOG_UNIMP, + "%s: unimplemented [0x%" HWADDR_PRIx "] <- 0x%" PRIx32 "\n", + __func__, addr, (uint32_t)value); +} + +static const MemoryRegionOps ppce500_ccsr_ops = { + .read = ppce500_ccsr_io_read, + .write = ppce500_ccsr_io_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; static void e500_ccsr_init(Object *obj) { PPCE500CCSRState *ccsr = CCSR(obj); - memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", - MPC8544_CCSRBAR_SIZE); + memory_region_init_io(&ccsr->ccsr_space, obj, &ppce500_ccsr_ops, obj, + "e500-ccsr", MPC8544_CCSRBAR_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(ccsr), &ccsr->ccsr_space); } diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 1f125ce841..ca4c231c9f 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -143,6 +143,9 @@ ppc_irq_cpu(const char *action) "%s" ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x" ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x" +ppce500_ccsr_io_read(uint32_t index, uint32_t val, uint8_t size) "[0x%" PRIx32 "] -> 0x%08x (size: 0x%" PRIu8 ")" +ppce500_ccsr_io_write(uint32_t index, uint32_t val, uint8_t size) "[0x%" PRIx32 "] <- 0x%08x (size: 0x%" PRIu8 ")" + # prep_systemio.c prep_systemio_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x" prep_systemio_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"
The CCSR space is just a container which is meant to be covered by platform device memory regions. However, QEMU only implements a subset of these devices. Add some logging to see which devices a guest attempts to access. Signed-off-by: Bernhard Beschow <shentey@gmail.com> --- hw/ppc/ppce500_ccsr.c | 33 +++++++++++++++++++++++++++++++-- hw/ppc/trace-events | 3 +++ 2 files changed, 34 insertions(+), 2 deletions(-)