| Message ID | 20240827053206.538814-1-kjain@linux.ibm.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | [1/3] perf vendor events power10: Update JSON/events | expand |
On Mon, Aug 26, 2024 at 10:33 PM Kajol Jain <kjain@linux.ibm.com> wrote: > > Update JSON/events for power10 platform with additional events. > > Signed-off-by: Kajol Jain <kjain@linux.ibm.com> For the series: Reviewed-by: Ian Rogers <irogers@google.com> Just to note, the moving of events in patches 2 and 3 is necessary as the filename sets the "topic" in perf list. I'm not sure the whole "topic" thing makes total sense and we may want to revisit it at some date. For example, AMD generally put the topic into the event name, the PMU gives a strong hint of "topic", etc. Thanks, Ian > --- > .../arch/powerpc/power10/datasource.json | 25 +++++++++++++++++++ > .../arch/powerpc/power10/frontend.json | 10 ++++++++ > .../pmu-events/arch/powerpc/power10/pmc.json | 5 ++++ > 3 files changed, 40 insertions(+) > > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/datasource.json b/tools/perf/pmu-events/arch/powerpc/power10/datasource.json > index 0eeaaf1a95b8..283284745d9c 100644 > --- a/tools/perf/pmu-events/arch/powerpc/power10/datasource.json > +++ b/tools/perf/pmu-events/arch/powerpc/power10/datasource.json > @@ -14,6 +14,31 @@ > "EventName": "PM_DATA_FROM_MEMORY", > "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss." > }, > + { > + "EventCode": "0x0000004080", > + "EventName": "PM_INST_FROM_L1", > + "BriefDescription": "An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched." > + }, > + { > + "EventCode": "0x000000026080", > + "EventName": "PM_L2_LD_MISS", > + "BriefDescription": "All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." > + }, > + { > + "EventCode": "0x000000026880", > + "EventName": "PM_L2_ST_MISS", > + "BriefDescription": "All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." > + }, > + { > + "EventCode": "0x010000046880", > + "EventName": "PM_L2_ST_HIT", > + "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." > + }, > + { > + "EventCode": "0x000000036880", > + "EventName": "PM_L2_INST_MISS", > + "BriefDescription": "All successful instruction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." > + }, > { > "EventCode": "0x000300000000C040", > "EventName": "PM_INST_FROM_L2", > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/frontend.json b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json > index 53660c279286..456971f60814 100644 > --- a/tools/perf/pmu-events/arch/powerpc/power10/frontend.json > +++ b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json > @@ -93,5 +93,15 @@ > "EventCode": "0x400FC", > "EventName": "PM_ITLB_MISS", > "BriefDescription": "Instruction TLB reload (after a miss), all page sizes. Includes only demand misses." > + }, > + { > + "EventCode": "0x00000040B8", > + "EventName": "PM_PRED_BR_TKN_COND_DIR", > + "BriefDescription": "A conditional branch finished with correctly predicted direction. Resolved taken." > + }, > + { > + "EventCode": "0x00000048B8", > + "EventName": "PM_PRED_BR_NTKN_COND_DIR", > + "BriefDescription": "A conditional branch finished with correctly predicted direction. Resolved not taken." > } > ] > diff --git a/tools/perf/pmu-events/arch/powerpc/power10/pmc.json b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json > index 0e0253d0e757..04732698d9b2 100644 > --- a/tools/perf/pmu-events/arch/powerpc/power10/pmc.json > +++ b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json > @@ -104,6 +104,11 @@ > "EventName": "PM_RUN_CYC", > "BriefDescription": "Processor cycles gated by the run latch." > }, > + { > + "EventCode": "0x200F8", > + "EventName": "PM_EXT_INT", > + "BriefDescription": "Cycles an external interrupt was active." > + }, > { > "EventCode": "0x30010", > "EventName": "PM_PMC2_OVERFLOW", > -- > 2.43.5 >
On 8/27/24 21:00, Ian Rogers wrote: > On Mon, Aug 26, 2024 at 10:33 PM Kajol Jain <kjain@linux.ibm.com> wrote: >> >> Update JSON/events for power10 platform with additional events. >> >> Signed-off-by: Kajol Jain <kjain@linux.ibm.com> > > For the series: > Reviewed-by: Ian Rogers <irogers@google.com> Hi Ian, Thanks for reviewing the patchset. > > Just to note, the moving of events in patches 2 and 3 is necessary as > the filename sets the "topic" in perf list. I'm not sure the whole > "topic" thing makes total sense and we may want to revisit it at some > date. For example, AMD generally put the topic into the event name, > the PMU gives a strong hint of "topic", etc. In my opinion, having topic helps in understanding the area to which given event belongs. And since we have multiple event categories in case of core PMU, Just having PMU name may not not sufficient. I will check further on adding topic to event name(which AMD is using), my concern is it will increase the event name size. As we already have bigger event names. But may be rather then picking topic from file name, we can add one separate field to define the topic in json and use that instead? Thanks, Kajol Jain > > Thanks, > Ian > >> --- >> .../arch/powerpc/power10/datasource.json | 25 +++++++++++++++++++ >> .../arch/powerpc/power10/frontend.json | 10 ++++++++ >> .../pmu-events/arch/powerpc/power10/pmc.json | 5 ++++ >> 3 files changed, 40 insertions(+) >> >> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/datasource.json b/tools/perf/pmu-events/arch/powerpc/power10/datasource.json >> index 0eeaaf1a95b8..283284745d9c 100644 >> --- a/tools/perf/pmu-events/arch/powerpc/power10/datasource.json >> +++ b/tools/perf/pmu-events/arch/powerpc/power10/datasource.json >> @@ -14,6 +14,31 @@ >> "EventName": "PM_DATA_FROM_MEMORY", >> "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss." >> }, >> + { >> + "EventCode": "0x0000004080", >> + "EventName": "PM_INST_FROM_L1", >> + "BriefDescription": "An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched." >> + }, >> + { >> + "EventCode": "0x000000026080", >> + "EventName": "PM_L2_LD_MISS", >> + "BriefDescription": "All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." >> + }, >> + { >> + "EventCode": "0x000000026880", >> + "EventName": "PM_L2_ST_MISS", >> + "BriefDescription": "All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." >> + }, >> + { >> + "EventCode": "0x010000046880", >> + "EventName": "PM_L2_ST_HIT", >> + "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." >> + }, >> + { >> + "EventCode": "0x000000036880", >> + "EventName": "PM_L2_INST_MISS", >> + "BriefDescription": "All successful instruction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." >> + }, >> { >> "EventCode": "0x000300000000C040", >> "EventName": "PM_INST_FROM_L2", >> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/frontend.json b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json >> index 53660c279286..456971f60814 100644 >> --- a/tools/perf/pmu-events/arch/powerpc/power10/frontend.json >> +++ b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json >> @@ -93,5 +93,15 @@ >> "EventCode": "0x400FC", >> "EventName": "PM_ITLB_MISS", >> "BriefDescription": "Instruction TLB reload (after a miss), all page sizes. Includes only demand misses." >> + }, >> + { >> + "EventCode": "0x00000040B8", >> + "EventName": "PM_PRED_BR_TKN_COND_DIR", >> + "BriefDescription": "A conditional branch finished with correctly predicted direction. Resolved taken." >> + }, >> + { >> + "EventCode": "0x00000048B8", >> + "EventName": "PM_PRED_BR_NTKN_COND_DIR", >> + "BriefDescription": "A conditional branch finished with correctly predicted direction. Resolved not taken." >> } >> ] >> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/pmc.json b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json >> index 0e0253d0e757..04732698d9b2 100644 >> --- a/tools/perf/pmu-events/arch/powerpc/power10/pmc.json >> +++ b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json >> @@ -104,6 +104,11 @@ >> "EventName": "PM_RUN_CYC", >> "BriefDescription": "Processor cycles gated by the run latch." >> }, >> + { >> + "EventCode": "0x200F8", >> + "EventName": "PM_EXT_INT", >> + "BriefDescription": "Cycles an external interrupt was active." >> + }, >> { >> "EventCode": "0x30010", >> "EventName": "PM_PMC2_OVERFLOW", >> -- >> 2.43.5 >>
On Tue, Aug 27, 2024 at 08:30:09AM -0700, Ian Rogers wrote: > On Mon, Aug 26, 2024 at 10:33 PM Kajol Jain <kjain@linux.ibm.com> wrote: > > > > Update JSON/events for power10 platform with additional events. > > > > Signed-off-by: Kajol Jain <kjain@linux.ibm.com> > > For the series: > Reviewed-by: Ian Rogers <irogers@google.com> Thanks, applied to perf-tools-next, - Arnaldo
diff --git a/tools/perf/pmu-events/arch/powerpc/power10/datasource.json b/tools/perf/pmu-events/arch/powerpc/power10/datasource.json index 0eeaaf1a95b8..283284745d9c 100644 --- a/tools/perf/pmu-events/arch/powerpc/power10/datasource.json +++ b/tools/perf/pmu-events/arch/powerpc/power10/datasource.json @@ -14,6 +14,31 @@ "EventName": "PM_DATA_FROM_MEMORY", "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss." }, + { + "EventCode": "0x0000004080", + "EventName": "PM_INST_FROM_L1", + "BriefDescription": "An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched." + }, + { + "EventCode": "0x000000026080", + "EventName": "PM_L2_LD_MISS", + "BriefDescription": "All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." + }, + { + "EventCode": "0x000000026880", + "EventName": "PM_L2_ST_MISS", + "BriefDescription": "All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." + }, + { + "EventCode": "0x010000046880", + "EventName": "PM_L2_ST_HIT", + "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." + }, + { + "EventCode": "0x000000036880", + "EventName": "PM_L2_INST_MISS", + "BriefDescription": "All successful instruction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." + }, { "EventCode": "0x000300000000C040", "EventName": "PM_INST_FROM_L2", diff --git a/tools/perf/pmu-events/arch/powerpc/power10/frontend.json b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json index 53660c279286..456971f60814 100644 --- a/tools/perf/pmu-events/arch/powerpc/power10/frontend.json +++ b/tools/perf/pmu-events/arch/powerpc/power10/frontend.json @@ -93,5 +93,15 @@ "EventCode": "0x400FC", "EventName": "PM_ITLB_MISS", "BriefDescription": "Instruction TLB reload (after a miss), all page sizes. Includes only demand misses." + }, + { + "EventCode": "0x00000040B8", + "EventName": "PM_PRED_BR_TKN_COND_DIR", + "BriefDescription": "A conditional branch finished with correctly predicted direction. Resolved taken." + }, + { + "EventCode": "0x00000048B8", + "EventName": "PM_PRED_BR_NTKN_COND_DIR", + "BriefDescription": "A conditional branch finished with correctly predicted direction. Resolved not taken." } ] diff --git a/tools/perf/pmu-events/arch/powerpc/power10/pmc.json b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json index 0e0253d0e757..04732698d9b2 100644 --- a/tools/perf/pmu-events/arch/powerpc/power10/pmc.json +++ b/tools/perf/pmu-events/arch/powerpc/power10/pmc.json @@ -104,6 +104,11 @@ "EventName": "PM_RUN_CYC", "BriefDescription": "Processor cycles gated by the run latch." }, + { + "EventCode": "0x200F8", + "EventName": "PM_EXT_INT", + "BriefDescription": "Cycles an external interrupt was active." + }, { "EventCode": "0x30010", "EventName": "PM_PMC2_OVERFLOW",
Update JSON/events for power10 platform with additional events. Signed-off-by: Kajol Jain <kjain@linux.ibm.com> --- .../arch/powerpc/power10/datasource.json | 25 +++++++++++++++++++ .../arch/powerpc/power10/frontend.json | 10 ++++++++ .../pmu-events/arch/powerpc/power10/pmc.json | 5 ++++ 3 files changed, 40 insertions(+)