diff mbox series

[for-9.2,v6,04/12] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device

Message ID 20240801154334.1009852-5-dbarboza@ventanamicro.com
State New
Headers show
Series riscv: QEMU RISC-V IOMMU Support | expand

Commit Message

Daniel Henrique Barboza Aug. 1, 2024, 3:43 p.m. UTC 
The RISC-V IOMMU PCI device we're going to add next is a reference
implementation of the riscv-iommu spec [1], which predicts that the
IOMMU can be implemented as a PCIe device.

However, RISC-V International (RVI), the entity that ratified the
riscv-iommu spec, didn't bother assigning a PCI ID for this IOMMU PCIe
implementation that the spec predicts. This puts us in an uncommon
situation because we want to add the reference IOMMU PCIe implementation
but we don't have a PCI ID for it.

Given that RVI doesn't provide a PCI ID for it we reached out to Red Hat
and Gerd Hoffman, and they were kind enough to give us a PCI ID for the
RISC-V IOMMU PCI reference device.

Thanks Red Hat and Gerd for this RISC-V IOMMU PCIe device ID.

[1] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0

Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
 docs/specs/pci-ids.rst | 2 ++
 include/hw/pci/pci.h   | 1 +
 2 files changed, 3 insertions(+)

Comments

Gerd Hoffmann Aug. 21, 2024, 11:34 a.m. UTC | #1 
On Thu, Aug 01, 2024 at 12:43:25PM GMT, Daniel Henrique Barboza wrote:
> The RISC-V IOMMU PCI device we're going to add next is a reference
> implementation of the riscv-iommu spec [1], which predicts that the
> IOMMU can be implemented as a PCIe device.
> 
> However, RISC-V International (RVI), the entity that ratified the
> riscv-iommu spec, didn't bother assigning a PCI ID for this IOMMU PCIe
> implementation that the spec predicts. This puts us in an uncommon
> situation because we want to add the reference IOMMU PCIe implementation
> but we don't have a PCI ID for it.
> 
> Given that RVI doesn't provide a PCI ID for it we reached out to Red Hat
> and Gerd Hoffman, and they were kind enough to give us a PCI ID for the
> RISC-V IOMMU PCI reference device.
> 
> Thanks Red Hat and Gerd for this RISC-V IOMMU PCIe device ID.
> 
> [1] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0
> 
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
diff mbox series

Patch

diff --git a/docs/specs/pci-ids.rst b/docs/specs/pci-ids.rst
index c0a3dec2e7..a89a9d0939 100644
--- a/docs/specs/pci-ids.rst
+++ b/docs/specs/pci-ids.rst
@@ -94,6 +94,8 @@  PCI devices (other than virtio):
   PCI ACPI ERST device (``-device acpi-erst``)
 1b36:0013
   PCI UFS device (``-device ufs``)
+1b36:0014
+  PCI RISC-V IOMMU device
 
 All these devices are documented in :doc:`index`.
 
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 14a869eeaa..bed62f1de2 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -116,6 +116,7 @@  extern bool pci_available;
 #define PCI_DEVICE_ID_REDHAT_PVPANIC     0x0011
 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST   0x0012
 #define PCI_DEVICE_ID_REDHAT_UFS         0x0013
+#define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014
 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
 
 #define FMT_PCIBUS                      PRIx64