| Message ID | 20240807000652.1417776-8-debug@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv support for control flow integrity extensions | expand |
On 8/7/24 10:06, Deepak Gupta wrote: > diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h > index 02afad608b..e6927ff847 100644 > --- a/target/riscv/cpu_user.h > +++ b/target/riscv/cpu_user.h > @@ -15,5 +15,6 @@ > #define xA6 16 > #define xA7 17 /* syscall number for RVI ABI */ > #define xT0 5 /* syscall number for RVE ABI */ > +#define xT2 7 Maybe just add them all? > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc > index 98e3806d5e..cbd7d5c395 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -36,6 +36,58 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a) > return true; > } > > +static bool trans_lpad(DisasContext *ctx, arg_lpad *a) > +{ > + bool lp_expected; > + /* zicfilp only supported on 32bit and 64bit */ > + if (get_xl(ctx) != MXL_RV32 && get_xl(ctx) != MXL_RV64) { > + return false; > + } Where does it say that? There doesn't seem to be anything in the spec that excludes rv128. > + lp_expected = ctx->fcfi_lp_expected; > + /* forward cfi not enabled or lp not expected, return false */ > + if (!ctx->fcfi_enabled) { > + return false; > + } Comments should explain why, not exactly mirror the code. In any case, better as: /* * If zicfilp not present, the encoding is a nop. * If forward cfi not enabled, the implementation is a nop. */ if (!ctx->fcfi_enabled) { return true; } No need to fall through into AUIPC to re-discover nop-ness. > + > + /* > + * If this is the first instruction of the TB, let the translator > + * know the landing pad requirement was satisfied. No need to bother > + * checking for CFI feature or enablement. > + */ Comment is strange, because you have just checked enablement. > + /* if lp was expected, do label check */ > + if (lp_expected) { > + TCGLabel *skip = gen_new_label(); > + TCGv tmp = tcg_temp_new(); > + tcg_gen_st_tl(tcg_constant_tl(NO_LP_EXPECTED), > + tcg_env, offsetof(CPURISCVState, elp)); This placement is wrong, according to the LPAD pseudocode. It must go last. > + tcg_gen_extract_tl(tmp, get_gpr(ctx, xT2, EXT_NONE), 12, 20); > + tcg_gen_brcondi_tl(TCG_COND_EQ, tcg_constant_tl(a->imm_cfi20), 0, skip); This one you check at translation time: if (a->imm_cfi20 != 0) > + tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->imm_cfi20, skip); > + gen_helper_raise_sw_check_excep(tcg_env, > + tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), > + tcg_constant_tl(LABEL_MISMATCH_LPAD), tcg_constant_tl(0)); > + gen_set_label(skip); > + } > + > + return true; > +} > + > static bool trans_auipc(DisasContext *ctx, arg_auipc *a) > { > TCGv target_pc = dest_gpr(ctx, a->rd); > @@ -75,6 +127,20 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) > gen_set_gpr(ctx, a->rd, succ_pc); > > tcg_gen_mov_tl(cpu_pc, target_pc); > + if (ctx->cfg_ptr->ext_zicfilp && ctx->fcfi_enabled) { No need to check ext_zicfilp, as fcfi_enabled includes that already. > + /* > + * Rely on a helper to check the forward CFI enable for the > + * current process mode. The alternatives would be (1) include > + * "fcfi enabled" in the cflags or (2) maintain a "fcfi > + * currently enabled" in tcg_env and emit TCG code to access > + * and test it. > + */ Comment is out of date. > + if (a->rs1 != xRA && a->rs1 != xT0 && a->rs1 != xT2) { > + tcg_gen_st_tl(tcg_constant_tl(LP_EXPECTED), > + tcg_env, offsetof(CPURISCVState, elp)); > + } > + } > + > lookup_and_goto_ptr(ctx); > > if (misaligned) { r~
On 8/7/24 10:06, Deepak Gupta wrote: > +++ b/target/riscv/insn32.decode > @@ -40,6 +40,7 @@ > %imm_z6 26:1 15:5 > %imm_mop5 30:1 26:2 20:2 > %imm_mop3 30:1 26:2 > +%imm_cfi20 12:20 > > # Argument sets: > &empty > @@ -123,7 +124,10 @@ sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm > > # *** RV32I Base Instruction Set *** > lui .................... ..... 0110111 @u > -auipc .................... ..... 0010111 @u > +{ > + lpad .................... 00000 0010111 %imm_cfi20 IMO, better as lpad imm:20 00000 0010111 without the %imm_cfi20 indirection. r~
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 1709564b32..2c585a63c2 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -592,6 +592,8 @@ typedef enum { typedef enum { MISSING_LPAD = 0, + MISALIGNED_LPAD = 1, + LABEL_MISMATCH_LPAD = 2, } cfi_violation_cause; /* hstatus CSR bits */ diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h index 02afad608b..e6927ff847 100644 --- a/target/riscv/cpu_user.h +++ b/target/riscv/cpu_user.h @@ -15,5 +15,6 @@ #define xA6 16 #define xA7 17 /* syscall number for RVI ABI */ #define xT0 5 /* syscall number for RVE ABI */ +#define xT2 7 #endif diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c45b8fa1d8..c963c59c8e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -40,6 +40,7 @@ %imm_z6 26:1 15:5 %imm_mop5 30:1 26:2 20:2 %imm_mop3 30:1 26:2 +%imm_cfi20 12:20 # Argument sets: &empty @@ -123,7 +124,10 @@ sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u -auipc .................... ..... 0010111 @u +{ + lpad .................... 00000 0010111 %imm_cfi20 + auipc .................... ..... 0010111 @u +} jal .................... ..... 1101111 @j jalr ............ ..... 000 ..... 1100111 @i beq ....... ..... ..... 000 ..... 1100011 @b diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 98e3806d5e..cbd7d5c395 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -36,6 +36,58 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a) return true; } +static bool trans_lpad(DisasContext *ctx, arg_lpad *a) +{ + bool lp_expected; + /* zicfilp only supported on 32bit and 64bit */ + if (get_xl(ctx) != MXL_RV32 && get_xl(ctx) != MXL_RV64) { + return false; + } + + lp_expected = ctx->fcfi_lp_expected; + /* forward cfi not enabled or lp not expected, return false */ + if (!ctx->fcfi_enabled) { + return false; + } + + /* + * If this is the first instruction of the TB, let the translator + * know the landing pad requirement was satisfied. No need to bother + * checking for CFI feature or enablement. + */ + + if (ctx->base.pc_next == ctx->base.pc_first) { + ctx->fcfi_lp_expected = false; + /* If landing pad was expected, PC must be 4 byte aligned */ + if (lp_expected && ((ctx->base.pc_next) & 0x3)) { + /* + * misaligned, according to spec we should raise sw check exception + */ + gen_helper_raise_sw_check_excep(tcg_env, + tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), + tcg_constant_tl(MISALIGNED_LPAD), tcg_constant_tl(0)); + return true; + } + } + + /* if lp was expected, do label check */ + if (lp_expected) { + TCGLabel *skip = gen_new_label(); + TCGv tmp = tcg_temp_new(); + tcg_gen_st_tl(tcg_constant_tl(NO_LP_EXPECTED), + tcg_env, offsetof(CPURISCVState, elp)); + tcg_gen_extract_tl(tmp, get_gpr(ctx, xT2, EXT_NONE), 12, 20); + tcg_gen_brcondi_tl(TCG_COND_EQ, tcg_constant_tl(a->imm_cfi20), 0, skip); + tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->imm_cfi20, skip); + gen_helper_raise_sw_check_excep(tcg_env, + tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), + tcg_constant_tl(LABEL_MISMATCH_LPAD), tcg_constant_tl(0)); + gen_set_label(skip); + } + + return true; +} + static bool trans_auipc(DisasContext *ctx, arg_auipc *a) { TCGv target_pc = dest_gpr(ctx, a->rd); @@ -75,6 +127,20 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) gen_set_gpr(ctx, a->rd, succ_pc); tcg_gen_mov_tl(cpu_pc, target_pc); + if (ctx->cfg_ptr->ext_zicfilp && ctx->fcfi_enabled) { + /* + * Rely on a helper to check the forward CFI enable for the + * current process mode. The alternatives would be (1) include + * "fcfi enabled" in the cflags or (2) maintain a "fcfi + * currently enabled" in tcg_env and emit TCG code to access + * and test it. + */ + if (a->rs1 != xRA && a->rs1 != xT0 && a->rs1 != xT2) { + tcg_gen_st_tl(tcg_constant_tl(LP_EXPECTED), + tcg_env, offsetof(CPURISCVState, elp)); + } + } + lookup_and_goto_ptr(ctx); if (misaligned) {
Implements setting lp expected when `jalr` is encountered and implements `lpad` instruction of zicfilp. `lpad` instruction is taken out of auipc x0, <imm_20>. This is an existing HINTNOP space. If `lpad` is target of an indirect branch, cpu checks for 20 bit value in x7 upper with 20 bit value embedded in `lpad`. If they don't match, cpu raises a sw check exception with tval = 2. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Co-developed-by: Jim Shu <jim.shu@sifive.com> Co-developed-by: Andy Chiu <andy.chiu@sifive.com> --- target/riscv/cpu_bits.h | 2 + target/riscv/cpu_user.h | 1 + target/riscv/insn32.decode | 6 ++- target/riscv/insn_trans/trans_rvi.c.inc | 66 +++++++++++++++++++++++++ 4 files changed, 74 insertions(+), 1 deletion(-)