| Message ID | A9667DDFB95DB7438FA9D7D576C3D87E072009@SHSMSX101.ccr.corp.intel.com |
|---|---|
| State | New |
| Headers | show |
On 02/20/2012 01:25 AM, Zhang, Yang Z wrote: > When time base is 32kHz, the update cycle takes 1984us at the end > of every second. And the update cycle begins 244us later after UIP > is set. So the UIP is set in 2228us at end of every second. I think we can keep UIP set only for 244us, since our update cycle is instantaneous. Otherwise looks good, thanks! Paolo > Signed-off-by: Yang Zhang <yang.z.zhang@intel.com> > > --- > hw/mc146818rtc.c | 26 ++++++++++++++++++++++++++ > 1 files changed, 26 insertions(+), 0 deletions(-) > > diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c > index 2445c6b..d4be8e9 100644 > --- a/hw/mc146818rtc.c > +++ b/hw/mc146818rtc.c > @@ -601,6 +601,29 @@ static void rtc_calibrate_time(RTCState *s) > s->current_tm = *ret; > } > > +static int update_in_progress(RTCState *s) > +{ > + struct timeval tv_now; > + int64_t host_usec, offset_usec, guest_usec; > + > + if (s->cmos_data[RTC_REG_B] & REG_B_SET) { > + return 0; > + } > + > + gettimeofday(&tv_now, NULL); > + host_usec = tv_now.tv_sec * USEC_PER_SEC + tv_now.tv_usec; > + offset_usec = s->offset_sec * USEC_PER_SEC + s->offset_usec; > + guest_usec = host_usec + offset_usec; > + > + /* UIP bit will be set at last 2228us of every second. > + * Only consider oscillator in 32.768kHz*/ > + if ((guest_usec % USEC_PER_SEC) >= (USEC_PER_SEC - 2228)) { > + return 1; > + }
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index 2445c6b..d4be8e9 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -601,6 +601,29 @@ static void rtc_calibrate_time(RTCState *s) s->current_tm = *ret; } +static int update_in_progress(RTCState *s) +{ + struct timeval tv_now; + int64_t host_usec, offset_usec, guest_usec; + + if (s->cmos_data[RTC_REG_B] & REG_B_SET) { + return 0; + } + + gettimeofday(&tv_now, NULL); + host_usec = tv_now.tv_sec * USEC_PER_SEC + tv_now.tv_usec; + offset_usec = s->offset_sec * USEC_PER_SEC + s->offset_usec; + guest_usec = host_usec + offset_usec; + + /* UIP bit will be set at last 2228us of every second. + * Only consider oscillator in 32.768kHz*/ + if ((guest_usec % USEC_PER_SEC) >= (USEC_PER_SEC - 2228)) { + return 1; + } + + return 0; +} + static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) { RTCState *s = opaque; @@ -622,6 +645,9 @@ static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) break; case RTC_REG_A: ret = s->cmos_data[s->cmos_index]; + if (update_in_progress(s)) { + ret |= REG_A_UIP; + } break; case RTC_REG_C: ret = s->cmos_data[s->cmos_index];
The UIP(update in progress) is set when RTC is updating. We only consider the normal oscillator(32Khz) mode. When time base is 32kHz, the update cycle takes 1984us at the end of every second. And the update cycle begins 244us later after UIP is set. So the UIP is set in 2228us at end of every second. Signed-off-by: Yang Zhang <yang.z.zhang@intel.com> --- hw/mc146818rtc.c | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) -- 1.7.1