| Message ID | 20240105221327.176764-3-atishp@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add ISA extension smcntrpmf support | expand |
On 1/5/24 19:13, Atish Patra wrote: > From: Kaiwen Xue <kaiwenx@rivosinc.com> > > This adds the properties for ISA extension smcntrpmf. Patches > implementing it will follow. > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 83c7c0cf07be..ea34ff2ae983 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -148,6 +148,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > + ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), > ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), Sorry for not noticing this in the previous version. I believe we want the "smcntrpmf" entry to be right after "smaia" because the isa_edata_arr[] ordering matters when building the riscv,isa string in riscv_isa_string_ext(). Thanks, Daniel > @@ -1296,6 +1297,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit) > const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > /* Defaults for standard extensions */ > MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), > + MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), > MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), > MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), > MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index f4605fb190b9..00c34fdd3209 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -72,6 +72,7 @@ struct RISCVCPUConfig { > bool ext_zihpm; > bool ext_smstateen; > bool ext_sstc; > + bool ext_smcntrpmf; > bool ext_svadu; > bool ext_svinval; > bool ext_svnapot;
On Mon, Jan 8, 2024 at 10:10 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > > > On 1/5/24 19:13, Atish Patra wrote: > > From: Kaiwen Xue <kaiwenx@rivosinc.com> > > > > This adds the properties for ISA extension smcntrpmf. Patches > > implementing it will follow. > > > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > > --- > > target/riscv/cpu.c | 2 ++ > > target/riscv/cpu_cfg.h | 1 + > > 2 files changed, 3 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 83c7c0cf07be..ea34ff2ae983 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -148,6 +148,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > > + ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > > ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), > > ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), > > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > > Sorry for not noticing this in the previous version. I believe we want the "smcntrpmf" > entry to be right after "smaia" because the isa_edata_arr[] ordering matters when > building the riscv,isa string in riscv_isa_string_ext(). > Oops. Thanks for catching that. Fixed in v4. > > Thanks, > > Daniel > > > @@ -1296,6 +1297,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit) > > const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > > /* Defaults for standard extensions */ > > MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), > > + MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), > > MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), > > MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), > > MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > > index f4605fb190b9..00c34fdd3209 100644 > > --- a/target/riscv/cpu_cfg.h > > +++ b/target/riscv/cpu_cfg.h > > @@ -72,6 +72,7 @@ struct RISCVCPUConfig { > > bool ext_zihpm; > > bool ext_smstateen; > > bool ext_sstc; > > + bool ext_smcntrpmf; > > bool ext_svadu; > > bool ext_svinval; > > bool ext_svnapot;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 83c7c0cf07be..ea34ff2ae983 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -148,6 +148,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), + ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), @@ -1296,6 +1297,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit) const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), + MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index f4605fb190b9..00c34fdd3209 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -72,6 +72,7 @@ struct RISCVCPUConfig { bool ext_zihpm; bool ext_smstateen; bool ext_sstc; + bool ext_smcntrpmf; bool ext_svadu; bool ext_svinval; bool ext_svnapot;