diff mbox series

[v3,3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

Message ID 20240103185716.1790546-4-me@deliversmonkey.space
State New
Headers show
Series Pointer Masking update for Zjpm v0.8 | expand

Commit Message

Alexey Baturo Jan. 3, 2024, 6:57 p.m. UTC 
From: Alexey Baturo <baturo.alexey@gmail.com>

Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
 target/riscv/cpu.h        |  4 +++
 target/riscv/cpu_helper.c | 54 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

Comments

Deepak Gupta Jan. 5, 2024, 12:46 a.m. UTC | #1 
On Wed, Jan 3, 2024 at 10:59 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
> +
> +bool riscv_cpu_bare_mode(CPURISCVState *env)
> +{
> +    int satp_mode = 0;
> +#ifndef CONFIG_USER_ONLY
> +    if (riscv_cpu_mxl(env) == MXL_RV32) {
> +        satp_mode = get_field(env->satp, SATP32_MODE);
> +    } else {
> +        satp_mode = get_field(env->satp, SATP64_MODE);
> +    }
> +#endif
> +    return (satp_mode == VM_1_10_MBARE);
> +}
> +

Assume the CPU was in S or U with satp = non-bare mode but then a
transfer to M-mode happened.
In that case, even though the CPU is in M mode, the above function
will return non-bare mode and enforce
signed extension on M mode pointer masking (if enabled).

right or am I missing something here?
Alexey Baturo Jan. 5, 2024, 7:33 a.m. UTC | #2 
I think you're right, thanks.
I'll add a check for M-mode as well and I guess I'll have to rename the
function.
Any ideas on the proper and self-describing name?

Thanks

пт, 5 янв. 2024 г. в 03:46, Deepak Gupta <debug@rivosinc.com>:

> On Wed, Jan 3, 2024 at 10:59 AM Alexey Baturo <baturo.alexey@gmail.com>
> wrote:
> > +
> > +bool riscv_cpu_bare_mode(CPURISCVState *env)
> > +{
> > +    int satp_mode = 0;
> > +#ifndef CONFIG_USER_ONLY
> > +    if (riscv_cpu_mxl(env) == MXL_RV32) {
> > +        satp_mode = get_field(env->satp, SATP32_MODE);
> > +    } else {
> > +        satp_mode = get_field(env->satp, SATP64_MODE);
> > +    }
> > +#endif
> > +    return (satp_mode == VM_1_10_MBARE);
> > +}
> > +
>
> Assume the CPU was in S or U with satp = non-bare mode but then a
> transfer to M-mode happened.
> In that case, even though the CPU is in M mode, the above function
> will return non-bare mode and enforce
> signed extension on M mode pointer masking (if enabled).
>
> right or am I missing something here?
>
Deepak Gupta Jan. 5, 2024, 6:13 p.m. UTC | #3 
On Fri, Jan 05, 2024 at 10:33:40AM +0300, Alexey Baturo wrote:
>I think you're right, thanks.
>I'll add a check for M-mode as well and I guess I'll have to rename the
>function.
>Any ideas on the proper and self-describing name?

Since all we care for is whether virtual memory is enabled and in effect or not.
Some suggestions below
`
bool riscv_cpu_mmu_enabled
bool riscv_cpu_paging_enabled
bool riscv_cpu_virt_mem_enabled


>
>Thanks
>
>пт, 5 янв. 2024 г. в 03:46, Deepak Gupta <debug@rivosinc.com>:
>
>> On Wed, Jan 3, 2024 at 10:59 AM Alexey Baturo <baturo.alexey@gmail.com>
>> wrote:
>> > +
>> > +bool riscv_cpu_bare_mode(CPURISCVState *env)
>> > +{
>> > +    int satp_mode = 0;
>> > +#ifndef CONFIG_USER_ONLY
>> > +    if (riscv_cpu_mxl(env) == MXL_RV32) {
>> > +        satp_mode = get_field(env->satp, SATP32_MODE);
>> > +    } else {
>> > +        satp_mode = get_field(env->satp, SATP64_MODE);
>> > +    }
>> > +#endif
>> > +    return (satp_mode == VM_1_10_MBARE);
>> > +}
>> > +
>>
>> Assume the CPU was in S or U with satp = non-bare mode but then a
>> transfer to M-mode happened.
>> In that case, even though the CPU is in M mode, the above function
>> will return non-bare mode and enforce
>> signed extension on M mode pointer masking (if enabled).
>>
>> right or am I missing something here?
>>
diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bd379ee653..c607a94bba 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -672,6 +672,10 @@  static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
                           uint64_t *cs_base, uint32_t *pflags);
 
+bool riscv_cpu_bare_mode(CPURISCVState *env);
+RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
+int riscv_pm_get_pmlen(RISCVPmPmm pmm);
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a3d477d226..4c34e12ee3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -139,6 +139,60 @@  void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pflags = flags;
 }
 
+RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
+{
+    int pmm = 0;
+#ifndef CONFIG_USER_ONLY
+    int priv_mode = cpu_address_mode(env);
+    /* Get current PMM field */
+    switch (priv_mode) {
+    case PRV_M:
+        pmm = riscv_cpu_cfg(env)->ext_smmpm ?
+                  get_field(env->mseccfg, MSECCFG_PMM) : PMM_FIELD_DISABLED;
+        break;
+    case PRV_S:
+        pmm = riscv_cpu_cfg(env)->ext_smnpm ?
+                  get_field(env->menvcfg, MENVCFG_PMM) : PMM_FIELD_DISABLED;
+        break;
+    case PRV_U:
+        pmm = riscv_cpu_cfg(env)->ext_ssnpm ?
+                  get_field(env->senvcfg, SENVCFG_PMM) : PMM_FIELD_DISABLED;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+#endif
+    return pmm;
+}
+
+bool riscv_cpu_bare_mode(CPURISCVState *env)
+{
+    int satp_mode = 0;
+#ifndef CONFIG_USER_ONLY
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
+        satp_mode = get_field(env->satp, SATP32_MODE);
+    } else {
+        satp_mode = get_field(env->satp, SATP64_MODE);
+    }
+#endif
+    return (satp_mode == VM_1_10_MBARE);
+}
+
+int riscv_pm_get_pmlen(RISCVPmPmm pmm)
+{
+    switch (pmm) {
+    case PMM_FIELD_DISABLED:
+        return 0;
+    case PMM_FIELD_PMLEN7:
+        return 7;
+    case PMM_FIELD_PMLEN16:
+        return 16;
+    default:
+        g_assert_not_reached();
+    }
+    return -1;
+}
+
 #ifndef CONFIG_USER_ONLY
 
 /*