| Message ID | 20231221113628.41038-3-vadim.shakirov@syntacore.com |
|---|---|
| State | New |
| Headers | show |
| Series | Added the ability to delegate LCOFI to VS | expand |
On 12/21/23 08:36, Vadim Shakirov wrote: > In the AIA specification in the paragraph "Virtual interrupts for VS level" > it is indicated for interrupts 13-63: if the bit in hideleg is enabled, > then the corresponding vsip and vsie bits are aliases to sip and sie > > Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/csr.c | 36 ++++++++++++++++++++++++++---------- > 1 file changed, 26 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 36f807d5f6..46a5d0c69a 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1129,7 +1129,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, > > static const uint64_t delegable_ints = S_MODE_INTERRUPTS | > VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; > -static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; > +static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; > static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | > HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; > #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ > @@ -1167,7 +1167,7 @@ static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP | > static const target_ulong hip_writable_mask = MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | > MIP_VSEIP; > -static const target_ulong vsip_writable_mask = MIP_VSSIP; > +static const target_ulong vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; > > const bool valid_vm_1_10_32[16] = { > [VM_1_10_MBARE] = true, > @@ -2416,20 +2416,34 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno, > return write_mstatus(env, CSR_MSTATUS, newval); > } > > + > +static uint64_t vsi_to_mi(uint64_t vsi) > +{ > + uint64_t mi; > + > + mi = (vsi & (VS_MODE_INTERRUPTS >> 1)) << 1; > + mi |= vsi & LOCAL_INTERRUPTS; > + > + return mi; > +} > + > static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, > uint64_t *ret_val, > uint64_t new_val, uint64_t wr_mask) > { > RISCVException ret; > - uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; > + uint64_t rval, mask = env->hideleg & (VS_MODE_INTERRUPTS | > + LOCAL_INTERRUPTS); > > /* Bring VS-level bits to correct position */ > - new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; > - wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; > + new_val = vsi_to_mi(new_val); > + wr_mask = vsi_to_mi(wr_mask); > > ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); > + > if (ret_val) { > - *ret_val = (rval & mask) >> 1; > + *ret_val = (rval & (env->hideleg & VS_MODE_INTERRUPTS)) >> 1; > + *ret_val |= rval & (env->hideleg & LOCAL_INTERRUPTS); > } > > return ret; > @@ -2630,16 +2644,18 @@ static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, > uint64_t new_val, uint64_t wr_mask) > { > RISCVException ret; > - uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; > + uint64_t rval, mask = env->hideleg & (VS_MODE_INTERRUPTS | > + LOCAL_INTERRUPTS); > > /* Bring VS-level bits to correct position */ > - new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; > - wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; > + new_val = vsi_to_mi(new_val); > + wr_mask = vsi_to_mi(wr_mask); > > ret = rmw_mip64(env, csrno, &rval, new_val, > wr_mask & mask & vsip_writable_mask); > if (ret_val) { > - *ret_val = (rval & mask) >> 1; > + *ret_val = (rval & (env->hideleg & VS_MODE_INTERRUPTS)) >> 1; > + *ret_val |= rval & (env->hideleg & LOCAL_INTERRUPTS); > } > > return ret;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 36f807d5f6..46a5d0c69a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1129,7 +1129,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, static const uint64_t delegable_ints = S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; -static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; +static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ @@ -1167,7 +1167,7 @@ static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP | static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; -static const target_ulong vsip_writable_mask = MIP_VSSIP; +static const target_ulong vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; const bool valid_vm_1_10_32[16] = { [VM_1_10_MBARE] = true, @@ -2416,20 +2416,34 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno, return write_mstatus(env, CSR_MSTATUS, newval); } + +static uint64_t vsi_to_mi(uint64_t vsi) +{ + uint64_t mi; + + mi = (vsi & (VS_MODE_INTERRUPTS >> 1)) << 1; + mi |= vsi & LOCAL_INTERRUPTS; + + return mi; +} + static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; + uint64_t rval, mask = env->hideleg & (VS_MODE_INTERRUPTS | + LOCAL_INTERRUPTS); /* Bring VS-level bits to correct position */ - new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; - wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; + new_val = vsi_to_mi(new_val); + wr_mask = vsi_to_mi(wr_mask); ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); + if (ret_val) { - *ret_val = (rval & mask) >> 1; + *ret_val = (rval & (env->hideleg & VS_MODE_INTERRUPTS)) >> 1; + *ret_val |= rval & (env->hideleg & LOCAL_INTERRUPTS); } return ret; @@ -2630,16 +2644,18 @@ static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; + uint64_t rval, mask = env->hideleg & (VS_MODE_INTERRUPTS | + LOCAL_INTERRUPTS); /* Bring VS-level bits to correct position */ - new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; - wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; + new_val = vsi_to_mi(new_val); + wr_mask = vsi_to_mi(wr_mask); ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask & vsip_writable_mask); if (ret_val) { - *ret_val = (rval & mask) >> 1; + *ret_val = (rval & (env->hideleg & VS_MODE_INTERRUPTS)) >> 1; + *ret_val |= rval & (env->hideleg & LOCAL_INTERRUPTS); } return ret;
In the AIA specification in the paragraph "Virtual interrupts for VS level" it is indicated for interrupts 13-63: if the bit in hideleg is enabled, then the corresponding vsip and vsie bits are aliases to sip and sie Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com> --- target/riscv/csr.c | 36 ++++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-)