| Message ID | 20231103134629.561732-9-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | rv64i and rva22u64 CPUs, RVA22U64 profile support | expand |
On Nov 3, 2023, at 21:46, Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > QEMU implements all possible extensions of this profile. All the so > called 'synthetic extensions' described in the profile that are cache > related are ignored/assumed enabled (Za64rs, Zic64b, Ziccif, Ziccrse, > Ziccamoa, Zicclsm) since we do not implement a cache model. > +/* > + * RVA22U64 defines some 'named features' or 'synthetic extensions' > + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa > + * and Zicclsm. We do not implement caching in QEMU so we'll consider > + * all these named features as always enabled. > + * > + * There's no riscv,isa update for them (nor for zic64b, despite it > + * having a cfg offset) at this moment. > + */ > +static RISCVCPUProfile RVA22U64 = { > + .name = "rva22u64", > + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU, > + .ext_offsets = { > + CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), > + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), > + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), > + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), > + CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), > + CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz), Hi Daniel, If the cache related extensions are `ignored/assumed enabled`, why don't we export them in `riscv,isa`? If we try to check the RVA22 profile in linux kernel running with qemu, the isa string is not match RVA22 profile. Thanks, Jerry
On Nov 3, 2023, at 21:46, Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > +/* > + * RVA22U64 defines some 'named features' or 'synthetic extensions' > + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa > + * and Zicclsm. We do not implement caching in QEMU so we'll consider > + * all these named features as always enabled. > + * Hi Daniel, If the cache related extensions are `ignored/assumed enabled`, why don't we export them in `riscv,isa`? If we try to check the RVA22 profile in linux kernel running with qemu, the isa string is not match RVA22 profile. Thanks, Jerry
On 11/21/23 05:13, Jerry Shih wrote: > On Nov 3, 2023, at 21:46, Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: >> >> +/* >> + * RVA22U64 defines some 'named features' or 'synthetic extensions' >> + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa >> + * and Zicclsm. We do not implement caching in QEMU so we'll consider >> + * all these named features as always enabled. >> + * > > Hi Daniel, > > If the cache related extensions are `ignored/assumed enabled`, why don't > we export them in `riscv,isa`? These aren't extensions, but 'named features'. They don't have a riscv,isa. There's no DT bindings for them. > If we try to check the RVA22 profile in linux kernel running with qemu, the > isa string is not match RVA22 profile. The kernel would check profile compatibility by matching the riscv,isa of the actual extensions, as expected, but then it would need to check these 'named features' in other fashion. For example, in patch 06, zic64b would be asserted by checking if all block sizes are 64 bytes. I agree that this is over-complicated and checking everything in riscv,isa would make things easier. For now these named extensions don't have DT bindings, thus we can't add them to the DT. The kernel doesn't seem to care about their existence in the DT either. TBH a better place for this discussion is the kernel mailing list. Thanks, Daniel > > Thanks, > Jerry
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e3ee16a25..5b78b7496d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1487,6 +1487,38 @@ Property riscv_cpu_options[] = { DEFINE_PROP_END_OF_LIST(), }; +/* + * RVA22U64 defines some 'named features' or 'synthetic extensions' + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa + * and Zicclsm. We do not implement caching in QEMU so we'll consider + * all these named features as always enabled. + * + * There's no riscv,isa update for them (nor for zic64b, despite it + * having a cfg offset) at this moment. + */ +static RISCVCPUProfile RVA22U64 = { + .name = "rva22u64", + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU, + .ext_offsets = { + CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), + CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), + CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz), + + /* mandatory named features for this profile */ + CPU_CFG_OFFSET(zic64b), + + RISCV_PROFILE_EXT_LIST_END + } +}; + +RISCVCPUProfile *riscv_profiles[] = { + &RVA22U64, + NULL, +}; + static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf12f34082..e4d5d69207 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,6 +66,18 @@ const char *riscv_get_misa_ext_description(uint32_t bit); #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) +typedef struct riscv_cpu_profile { + const char *name; + uint32_t misa_ext; + bool enabled; + bool user_set; + const int32_t ext_offsets[]; +} RISCVCPUProfile; + +#define RISCV_PROFILE_EXT_LIST_END -1 + +extern RISCVCPUProfile *riscv_profiles[]; + /* Privileged specification version */ enum { PRIV_VERSION_1_10_0 = 0,