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[00/11] Various updates for the Cadence GEM model

Message ID 20231017194422.4124691-1-luc.michel@amd.com
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Series Various updates for the Cadence GEM model | expand

Message

Luc Michel Oct. 17, 2023, 7:44 p.m. UTC 
Hi,

This series brings small changes to the Cadence GEM Ethernet model.
There is (almost) no behaviour change.

Patches 1 to 9 replace handcrafted defines with the use of REG32 and
FIELDS macros for register and fields declarations.

Patch 10 fixes PHY accesses so that they are done only on a write to the
PHYMNTNC register (as the real hardware does).

Patch 11 fixes a potential bug on hosts where unsigned would not be 32
bits.

Thanks,

Comments

Peter Maydell Oct. 27, 2023, 12:16 p.m. UTC | #1 
On Tue, 17 Oct 2023 at 20:44, Luc Michel <luc.michel@amd.com> wrote:
>
> Hi,
>
> This series brings small changes to the Cadence GEM Ethernet model.
> There is (almost) no behaviour change.
>
> Patches 1 to 9 replace handcrafted defines with the use of REG32 and
> FIELDS macros for register and fields declarations.
>
> Patch 10 fixes PHY accesses so that they are done only on a write to the
> PHYMNTNC register (as the real hardware does).
>
> Patch 11 fixes a potential bug on hosts where unsigned would not be 32
> bits.

Applied to target-arm.next, thanks.

Note to Sai for the future: in Reviewed-by: tags, as with
Signed-off-by: tags, the expected form is "Full Name <email@example.com>",
not just a bare email address. (I would actively ask for a change
on a signed-off-by line with an email alone, but for Reviewed-by
it's less significant.)

thanks
-- PMM